From a679756bdbff0fafb27fc686ffccb96d8c7072e2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 Jan 2022 13:44:45 +0000 Subject: [PATCH] see soc/fu/trap/main_stage.py trap() function, and: https://libre-soc.org/irclog/%23libre-soc.2022-01-18.log.html#t2022-01-18T13:21:25 bits of SRR1 need to be preserved on an interrupt, which means that PowerDecoder2 must schedule a read of SRR1. the Power ISA spec is extremely obscure and obtuse on which bits must be preserved, therefore it is just easier to copy microwatt behaviour --- src/openpower/decoder/power_decoder2.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index a8ff8532..cb054735 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1570,6 +1570,12 @@ class PowerDecode2(PowerDecodeSubset): # Note: OP_SC could actually be modified to just be a trap with m.If((do_out.insn_type == MicrOp.OP_TRAP) | (do_out.insn_type == MicrOp.OP_SC)): + # see fu/trap/main_stage.py trap() function: some bits of SRR1 + # need to be preserved, rather than just blithely overwrite MSR. + # following microwatt, here. + # TRAP read fast2 = SRR1 + comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1) # SRR1 + comb += e_out.read_fast2.ok.eq(1) # TRAP write fast1 = SRR0 comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0) # SRR0 comb += e_out.write_fast1.ok.eq(1) -- 2.30.2