From a67c21910a83dbd7abdcdd106c0bae2d78baf212 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Sep 2022 09:06:58 +0100 Subject: [PATCH] comments --- src/openpower/decoder/isa/caller.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 3a0452fc..2f212958 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -66,6 +66,9 @@ special_sprs = { 'VRSAVE': 256} +# rrright. this is here basically because the compiler pywriter returns +# results in a specific priority order. to make sure regs match up they +# need partial sorting. sigh. REG_SORT_ORDER = { # TODO (lkcl): adjust other registers that should be in a particular order # probably CA, CA32, and CR -- 2.30.2