From a68921edcad6632ee8feb75baafaee309885e5a0 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 4 Sep 2021 18:20:54 +1000 Subject: [PATCH] core: Fix mcrxrx, addpcis and bpermd - mcrxrx put the bits in the wrong order - addpcis was setting CR0 if the instruction bit 0 = 1, which it shouldn't - bpermd was producing 0 always and additionally had the wrong bit numbering Signed-off-by: Paul Mackerras --- decode1.vhdl | 4 ++-- execute1.vhdl | 2 +- logical.vhdl | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/decode1.vhdl b/decode1.vhdl index 5d0bdcb..0866b5b 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -166,7 +166,7 @@ architecture behaviour of decode1 is -- mcrf; and cr logical ops 2#000# => (ALU, NONE, OP_CROP, NONE, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- addpcis - 2#001# => (ALU, NONE, OP_ADD, CIA, CONST_DXHI4, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), + 2#001# => (ALU, NONE, OP_ADD, CIA, CONST_DXHI4, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- bclr, bcctr, bctar 2#100# => (ALU, NONE, OP_BCREG, SPR, SPR, NONE, SPR, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', NONE), -- isync @@ -210,7 +210,7 @@ architecture behaviour of decode1 is 2#1011001010# => (ALU, NONE, OP_ADD, RA, NONE, NONE, RT, '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), -- addzeo 2#0000011100# => (ALU, NONE, OP_AND, NONE, RB, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), -- and 2#0000111100# => (ALU, NONE, OP_AND, NONE, RB, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), -- andc - 2#0011111100# => (ALU, NONE, OP_BPERM, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- bperm + 2#0011111100# => (ALU, NONE, OP_BPERM, NONE, RB, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- bperm 2#0100111010# => (ALU, NONE, OP_BCD, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- cbcdtd 2#0100011010# => (ALU, NONE, OP_BCD, NONE, NONE, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- cdtbcd 2#0000000000# => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', NONE), -- cmp diff --git a/execute1.vhdl b/execute1.vhdl index 3f21757..ef89bf7 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -683,7 +683,7 @@ begin end if; when "100" => -- MCRXRX - newcrf := xerc_in.ov & xerc_in.ca & xerc_in.ov32 & xerc_in.ca32; + newcrf := xerc_in.ov & xerc_in.ov32 & xerc_in.ca & xerc_in.ca32; when others => end case; if current.insn_type = OP_MTCRF then diff --git a/logical.vhdl b/logical.vhdl index 6b6f202..b4ba116 100644 --- a/logical.vhdl +++ b/logical.vhdl @@ -153,7 +153,7 @@ begin for i in 0 to 7 loop j := i * 8; if rs(j+7 downto j+6) = "00" then - permute(i) <= rb(to_integer(unsigned(rs(j+5 downto j)))); + permute(i) <= rb(to_integer(unsigned(not rs(j+5 downto j)))); else permute(i) <= '0'; end if; -- 2.30.2