From d05435414de95ab24bd321db7cc5623edfc37117 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 19 Oct 2023 17:37:34 -0700 Subject: [PATCH 1/6] format code --- src/openpower/test/trap/trap_cases.py | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py index 1e91eb8b..dcab94f9 100644 --- a/src/openpower/test/trap/trap_cases.py +++ b/src/openpower/test/trap/trap_cases.py @@ -8,7 +8,6 @@ import random class TrapTestCase(TestAccumulatorBase): - def case_1_kaivb(self): # https://bugs.libre-soc.org/show_bug.cgi?id=859 lst = ["mtspr 850, 1", # KAIVB @@ -21,7 +20,7 @@ class TrapTestCase(TestAccumulatorBase): msr = 0xa000000000000003 self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, - initial_msr=msr) + initial_msr=msr) def case_2_kaivb_test(self): # https://bugs.libre-soc.org/show_bug.cgi?id=859 @@ -31,17 +30,17 @@ class TrapTestCase(TestAccumulatorBase): "tbegin.", # deliberately use illegal instruction ] initial_regs = [0] * 32 - initial_regs[1] = 1<<13 + initial_regs[1] = 1 << 13 initial_sprs = {'KAIVB': 0x12345678, } msr = 0xa000000000000003 e = ExpectedState(pc=0x2700) - e.intregs[1] = 1<<13 - e.msr = 0xa000000000000003 # TODO, not actually checked + e.intregs[1] = 1 << 13 + e.msr = 0xa000000000000003 # TODO, not actually checked self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, - initial_msr=msr, - expected=e) + initial_msr=msr, + expected=e) def case_0_hrfid(self): lst = ["hrfid"] @@ -55,12 +54,12 @@ class TrapTestCase(TestAccumulatorBase): lst = ["sc 0"] initial_regs = [0] * 32 initial_regs[1] = 1 - initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite + initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite # expected results: PC should be at 0xc00 (sc address) e = ExpectedState(pc=0xc00) e.intregs[1] = 1 e.sprs['SRR0'] = 4 # PC to return to: CIA+4 - e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return + e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return e.msr = 0x9000000000000001 # MSR changed to this by sc/trap self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, @@ -107,11 +106,11 @@ class TrapTestCase(TestAccumulatorBase): initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033} e = ExpectedState(pc=0x700) e.intregs[1] = 1 - e.msr = 0xb000000000001033 # TODO, not actually checked + e.msr = 0xb000000000001033 # TODO, not actually checked self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, - initial_msr=0xa000000000000003, - expected=e) + initial_msr=0xa000000000000003, + expected=e) def case_0_trap_eq_imm(self): insns = ["twi", "tdi"] @@ -149,7 +148,7 @@ class TrapTestCase(TestAccumulatorBase): initial_regs = [0] * 32 initial_regs[1] = 0xb000000000001033 self.add_case(Program(lst, bigendian), initial_regs, - initial_msr=0xa000000000000003) + initial_msr=0xa000000000000003) def case_4_mtmsrd_0(self): lst = ["mtmsrd 1,0"] @@ -202,4 +201,3 @@ class TrapTestCase(TestAccumulatorBase): "mtmsr 1,1"] # should not get executed initial_regs = [0] * 32 self.add_case(Program(lst, bigendian), initial_regs) - -- 2.30.2 From 5bd2d42ff69d976f3405f3f74aaac855617d85fd Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 19 Oct 2023 17:49:04 -0700 Subject: [PATCH 2/6] fill in manually verified expected state for TrapTestCase.case_2_kaivb_test based on the Programming Note on left side of PowerISA v3.1B page 1289 (1315) --- src/openpower/test/trap/trap_cases.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py index dcab94f9..b90bf693 100644 --- a/src/openpower/test/trap/trap_cases.py +++ b/src/openpower/test/trap/trap_cases.py @@ -36,7 +36,10 @@ class TrapTestCase(TestAccumulatorBase): msr = 0xa000000000000003 e = ExpectedState(pc=0x2700) e.intregs[1] = 1 << 13 - e.msr = 0xa000000000000003 # TODO, not actually checked + e.sprs['SRR0'] = 0x4 + e.sprs['SRR1'] = 0xa000000000080003 + e.sprs['KAIVB'] = 0x2000 + e.msr = 0xa000000000000001 self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, initial_msr=msr, -- 2.30.2 From e0a4f19b2c90be84a77a4aa584c6d60e508d92f5 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 19 Oct 2023 18:00:55 -0700 Subject: [PATCH 3/6] skip broken test it wasn't obvious how to fix it, see https://bugs.libre-soc.org/show_bug.cgi?id=1193 --- src/openpower/test/trap/trap_cases.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py index b90bf693..2358c9db 100644 --- a/src/openpower/test/trap/trap_cases.py +++ b/src/openpower/test/trap/trap_cases.py @@ -3,7 +3,7 @@ from openpower.endian import bigendian from openpower.consts import MSR from openpower.test.state import ExpectedState -from openpower.test.common import TestAccumulatorBase +from openpower.test.common import TestAccumulatorBase, skip_case import random @@ -102,6 +102,8 @@ class TrapTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_sprs) + @skip_case("FIXME: add rest of expected state, expected pc looks wrong" + "see https://bugs.libre-soc.org/show_bug.cgi?id=1193") def case_2_rfid(self): lst = ["rfid"] initial_regs = [0] * 32 -- 2.30.2 From 6a816b8090d6b5ee6aa7d3caa09c2c1a2b087533 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 19 Oct 2023 18:17:20 -0700 Subject: [PATCH 4/6] Revert "fix bug introduced by having to revert unauthorized addition of" we need copy_assign_rhs See https://bugs.libre-soc.org/show_bug.cgi?id=1066 This reverts commit 9dab88318a2938f14873804d83bf85ef9ae2fb93. --- src/openpower/decoder/pseudo/parser.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py index 6a94e701..8610c284 100644 --- a/src/openpower/decoder/pseudo/parser.py +++ b/src/openpower/decoder/pseudo/parser.py @@ -405,8 +405,7 @@ class PowerParser: self.read_regs.add(toname) if name and name in self.gprs: self.write_regs.add(name) # add to list of regs to write - p[0] = self.Assign(autoassign, name, p[1], p[3], iea_mode, - p.slice[2]) + p[0] = Assign(autoassign, name, p[1], p[3], iea_mode) if name: self.declared_vars.add(name) -- 2.30.2 From ca57c0af2e6851c58e30b2e67fce4416996f69ae Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 19 Oct 2023 18:18:51 -0700 Subject: [PATCH 5/6] Revert "Revert "fix bug where pseudo-code assignments modify more than just the variable being assigned to"" we need copy_assign_rhs See https://bugs.libre-soc.org/show_bug.cgi?id=1066 This reverts commit bd3b54e83101217dc32da09083c6a3858fd7c600. --- src/openpower/decoder/helpers.py | 29 ++++++++++++++++++++++ src/openpower/decoder/pseudo/parser.py | 8 +++++- src/openpower/decoder/pseudo/pyfnwriter.py | 2 +- src/openpower/decoder/pseudo/pywriter.py | 2 +- 4 files changed, 38 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py index 99131c7f..2c937134 100644 --- a/src/openpower/decoder/helpers.py +++ b/src/openpower/decoder/helpers.py @@ -72,6 +72,35 @@ def EXTS128(value): return SelectableInt(exts(value.value, value.bits) & ((1 << 128)-1), 128) +def copy_assign_rhs(inp): + """ implicitly added function call to all assignment RHSes. + This copies the passed-in value so later assignments to parts of the + LHS don't modify the RHS if it's a SelectableInt. + + Example: + ``` + # this needs to copy the SelectableInt instance in RA + # not just assign a reference to it to A + A <- RA + A[0] <- 1 # if the copy wasn't performed, we just modified RA too! + ``` + """ + if isinstance(inp, (str, int)): + return inp + if isinstance(inp, (SelectableInt, FieldSelectableInt)): + return SelectableInt(inp) + if isinstance(inp, BFPState): + return BFPState(inp) + if isinstance(inp, SelectableMSB0Fraction): + return SelectableMSB0Fraction(inp) + if isinstance(inp, tuple): + return tuple(map(copy_assign_rhs, inp)) + if isinstance(inp, dict): + return {copy_assign_rhs(k): copy_assign_rhs(v) for k, v in inp.items()} + raise TypeError("tried to assign an unsupported type in pseudo-code", + repr(type(inp))) + + # signed version of MUL def MULS(a, b): if isinstance(b, int): diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py index 8610c284..8e913244 100644 --- a/src/openpower/decoder/pseudo/parser.py +++ b/src/openpower/decoder/pseudo/parser.py @@ -405,7 +405,13 @@ class PowerParser: self.read_regs.add(toname) if name and name in self.gprs: self.write_regs.add(name) # add to list of regs to write - p[0] = Assign(autoassign, name, p[1], p[3], iea_mode) + + # copy rhs -- see openpower.decoder.helpers.copy_assign_rhs()'s + # documentation for why we need this + copy_fn = ast.Name("copy_assign_rhs", ast.Load()) + rhs = ast.Call(copy_fn, (p[3],), []) + p[0] = self.Assign(autoassign, name, p[1], rhs, iea_mode, + p.slice[2]) if name: self.declared_vars.add(name) diff --git a/src/openpower/decoder/pseudo/pyfnwriter.py b/src/openpower/decoder/pseudo/pyfnwriter.py index 448b3e34..417706a4 100644 --- a/src/openpower/decoder/pseudo/pyfnwriter.py +++ b/src/openpower/decoder/pseudo/pyfnwriter.py @@ -21,7 +21,7 @@ header = """\ from openpower.decoder.isa.caller import inject from openpower.decoder.helpers import (ISACallerHelper, ne, eq, gt, ge, lt, le, ltu, gtu, length, - trunc_divs, trunc_rems, + trunc_divs, trunc_rems, copy_assign_rhs, ) from openpower.decoder.selectable_int import SelectableInt from openpower.decoder.selectable_int import selectconcat as concat diff --git a/src/openpower/decoder/pseudo/pywriter.py b/src/openpower/decoder/pseudo/pywriter.py index b0772935..6d436eef 100644 --- a/src/openpower/decoder/pseudo/pywriter.py +++ b/src/openpower/decoder/pseudo/pywriter.py @@ -23,7 +23,7 @@ header = """\ from openpower.decoder.isa.caller import inject, instruction_info from openpower.decoder.helpers import ( ne, eq, gt, ge, lt, le, ltu, gtu, length, - RANGE, + RANGE, copy_assign_rhs, ISACallerHelper, ) from openpower.decoder.selectable_int import SelectableInt -- 2.30.2 From a69f6426b866cf86a0ec8fb21dac58cb289cba2f Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 19 Oct 2023 18:57:00 -0700 Subject: [PATCH 6/6] Revert "skip broken test" requested by luke: https://bugs.libre-soc.org/show_bug.cgi?id=1193#c1 This reverts commit e0a4f19b2c90be84a77a4aa584c6d60e508d92f5. --- src/openpower/test/trap/trap_cases.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py index 2358c9db..b90bf693 100644 --- a/src/openpower/test/trap/trap_cases.py +++ b/src/openpower/test/trap/trap_cases.py @@ -3,7 +3,7 @@ from openpower.endian import bigendian from openpower.consts import MSR from openpower.test.state import ExpectedState -from openpower.test.common import TestAccumulatorBase, skip_case +from openpower.test.common import TestAccumulatorBase import random @@ -102,8 +102,6 @@ class TrapTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_sprs) - @skip_case("FIXME: add rest of expected state, expected pc looks wrong" - "see https://bugs.libre-soc.org/show_bug.cgi?id=1193") def case_2_rfid(self): lst = ["rfid"] initial_regs = [0] * 32 -- 2.30.2