From a6bb0222cf6da7f806f5b05d761ab84b588a1bd4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 25 Sep 2022 21:42:05 +0100 Subject: [PATCH] --- openpower/sv/biginteger/analysis.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 3d8bdbe05..5e03e1f2b 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -156,6 +156,21 @@ carry-propagation through multiple elements does not occur. With Scalar shift and rotate operations in the Power ISA already being complex and very comprehensive, it is hard to justify creating complex 3-in 2-out variants when a sequence of 3 simple instructions will suffice. +However it is reasonably justifiable to have a 3-in 1-out instruction +with an implicit source, based around the inner operation: + +``` + # r[i] = (un[i] >> s) | (un[i + 1] << (64 - s)); + t <- ROT128(RA || RA1, RB[58:63]) + RT <- t[64:127] +`` + +RA1 is implicitly (or explicitly, RC) greater than RA by one +scalar register number, and like the other operations below, +a 128/64 shift is performed, truncating to take the lower +64 bits. By taking a Vector source RA and assuming lower-numbered +registers are lower-significant digits in the biginteger operation +the entire biginteger source may be shifted by a scalar. For larger shift amounts beyond an element bitwidth standard register move operations may be used, or, if the shift amount is static, -- 2.30.2