From a6bf61c753d0302906772a47b81cc6e3d5ca3af6 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Fri, 30 Apr 2004 08:04:57 +0200 Subject: [PATCH] i386.md (atansf2, [...]): Move near atan2?f3 expanders. 2004-04-30 Uros Bizjak * config/i386/i386.md (atansf2, atandf2, atanxf2): Move near atan2?f3 expanders. From-SVN: r81326 --- gcc/ChangeLog | 5 +++ gcc/config/i386/i386.md | 78 ++++++++++++++++++++--------------------- 2 files changed, 44 insertions(+), 39 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 080affc413a..672ae8694a6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-04-30 Uros Bizjak + + * config/i386/i386.md (atansf2, atandf2, atanxf2): Move near + atan2?f3 expanders. + 2004-04-29 Nick Clifton Bug 14093 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index fbb39c1cd7a..3a87e712234 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15235,6 +15235,19 @@ DONE; }) +(define_expand "atandf2" + [(parallel [(set (match_operand:DF 0 "register_operand" "") + (unspec:DF [(match_dup 2) + (match_operand:DF 1 "register_operand" "")] + UNSPEC_FPATAN)) + (clobber (match_scratch:DF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + operands[2] = gen_reg_rtx (DFmode); + emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */ +}) + (define_insn "atan2sf3_1" [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:SF 2 "register_operand" "0") @@ -15260,6 +15273,19 @@ DONE; }) +(define_expand "atansf2" + [(parallel [(set (match_operand:SF 0 "register_operand" "") + (unspec:SF [(match_dup 2) + (match_operand:SF 1 "register_operand" "")] + UNSPEC_FPATAN)) + (clobber (match_scratch:SF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + operands[2] = gen_reg_rtx (SFmode); + emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */ +}) + (define_insn "atan2xf3_1" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 2 "register_operand" "0") @@ -15285,6 +15311,19 @@ DONE; }) +(define_expand "atanxf2" + [(parallel [(set (match_operand:XF 0 "register_operand" "") + (unspec:XF [(match_dup 2) + (match_operand:XF 1 "register_operand" "")] + UNSPEC_FPATAN)) + (clobber (match_scratch:XF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + operands[2] = gen_reg_rtx (XFmode); + emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ +}) + (define_expand "asindf2" [(set (match_dup 2) (float_extend:XF (match_operand:DF 1 "register_operand" ""))) @@ -15943,45 +15982,6 @@ operands[i] = gen_reg_rtx (XFmode); emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */ }) - -(define_expand "atansf2" - [(parallel [(set (match_operand:SF 0 "register_operand" "") - (unspec:SF [(match_dup 2) - (match_operand:SF 1 "register_operand" "")] - UNSPEC_FPATAN)) - (clobber (match_scratch:SF 3 ""))])] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" -{ - operands[2] = gen_reg_rtx (SFmode); - emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */ -}) - -(define_expand "atandf2" - [(parallel [(set (match_operand:DF 0 "register_operand" "") - (unspec:DF [(match_dup 2) - (match_operand:DF 1 "register_operand" "")] - UNSPEC_FPATAN)) - (clobber (match_scratch:DF 3 ""))])] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" -{ - operands[2] = gen_reg_rtx (DFmode); - emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */ -}) - -(define_expand "atanxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_dup 2) - (match_operand:XF 1 "register_operand" "")] - UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 ""))])] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" -{ - operands[2] = gen_reg_rtx (XFmode); - emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ -}) ;; Block operation instructions -- 2.30.2