From a6cad17d6d1c1f420e9e1d939605aebcd44d6c59 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 2 Oct 2021 20:59:21 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd.mdwn | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index d8e60039f..ad124adeb 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -146,6 +146,12 @@ raised. replacement for dsl.Module, called dsl.SIMDModule (or other). * **Monkey-patching dsl.Module**. This idea intrusively modifies dsl.Module with external functions. +* **Compilers / Macros**. On the basis that if this was VHDL or Verilog + one technique for creating SIMD variants of the required code would be + to use macro substitution or crude compilers to autogenerate the dynamic + SIMD from VHDL / Verilog templates, why not do exactly the same thing. + Design a SIMD langusge, write python in that, and have it output + nmigen HDL. All of these ideas, unfortunately, are extremely costly in many different ways: -- 2.30.2