From a6e6f8faa16612316b7f36d5f662f45a43850923 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 21 Dec 2018 12:26:49 +0000 Subject: [PATCH] hdl.mem: use different naming for array signals. It looks like [] is confusing gtkwave somehow. --- nmigen/hdl/mem.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index f60cdce..99ed6e1 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -35,7 +35,7 @@ class Memory: # Array of signals for simulation. self._array = Array() for addr, data in enumerate(self.init + [0 for _ in range(self.depth - len(self.init))]): - self._array.append(Signal(self.width, reset=data, name="{}[{}]".format(name, addr))) + self._array.append(Signal(self.width, reset=data, name="{}({})".format(name, addr))) def read_port(self, domain="sync", synchronous=True, transparent=True): if not synchronous and not transparent: -- 2.30.2