From a6eab3962ac143f0716bab896f5331808d56cf56 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Jun 2020 11:53:00 +0100 Subject: [PATCH] yield needed for unit tests to work (has to go) --- src/soc/fu/compunits/test/test_compunit.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index a62a4694..ee3c6fce 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -199,12 +199,12 @@ class TestRunner(FHDLTestCase): wr_rel_o = yield cu.wr.rel print ("before inputs, rd_rel, wr_rel: ", bin(rd_rel_o), bin(wr_rel_o)) - yield assert wr_rel_o == 0, "wr.rel %s must be zero. "\ "previous instr not written all regs\n"\ "respec %s" % \ (bin(wr_rel_o), cu.rwid[1]) yield from set_cu_inputs(cu, inp) + yield rd_rel_o = yield cu.rd.rel wr_rel_o = yield cu.wr.rel wrmask = yield cu.wrmask @@ -219,6 +219,11 @@ class TestRunner(FHDLTestCase): yield Settle() # get all outputs (one by one, just "because") res = yield from get_cu_outputs(cu, code) + wrmask = yield cu.wrmask + rd_rel_o = yield cu.rd.rel + wr_rel_o = yield cu.wr.rel + print ("after got outputs, rd_rel, wr_rel, wrmask: ", + bin(rd_rel_o), bin(wr_rel_o), bin(wrmask)) # wait for busy to go low while True: -- 2.30.2