From a6f78427de7eb99fda1dc19bf857e11a6510c904 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 20:56:29 +0100 Subject: [PATCH] more rename spr1/spr2 to fast1/fast2 --- src/soc/regfile/regfiles.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 7ed51a8a..5461eec5 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -70,13 +70,13 @@ class FastRegs(RegFileArray): super().__init__(64, 8) self.w_ports = {'nia': self.write_port("nia"), 'msr': self.write_port("dest2"), - 'spr1': self.write_port("dest3"), - 'spr2': self.write_port("dest4"), + 'fast1': self.write_port("dest3"), + 'fast2': self.write_port("dest4"), 'd_wr1': self.write_port("d_wr1")} self.r_ports = {'cia': self.read_port("src1"), 'msr': self.read_port("src2"), - 'spr1': self.read_port("src3"), - 'spr2': self.read_port("src4"), + 'fast1': self.read_port("src3"), + 'fast2': self.read_port("src4"), 'd_rd1': self.read_port("d_rd1")} -- 2.30.2