From a7100c27a38715e2171562465938331ca0af7714 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 6 Sep 2021 21:55:13 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 33ef7aad5..e0051edc1 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -21,10 +21,7 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: |dz |VLi| 01 | inv | CR-bit | normal mode | |sz |VLi| 01 | inv | dz Rc1 | VLSET mode | -Operations that actually produce or alter CR Field as a result do not -also in turn have an Rc=1 mode. However it makes no sense to try to test -the 4 bits of a CR Field for being equal or not equal to zero. Moreover, -the result is already in the form that is desired: it is a CR field. +Fields: There are two primary different types of CR operations: -- 2.30.2