From a710a0d7956529e200ec9198314ef71ca1522b12 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Feb 2019 15:13:13 +0000 Subject: [PATCH] add verilog conversion (commented out) --- src/add/nmigen_add_experiment.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index f0f3f735..e167c7bd 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -3,7 +3,7 @@ # 2013-12-12 from nmigen import Module, Signal, Cat -from nmigen.cli import main +from nmigen.cli import main, verilog class FPNum: @@ -362,9 +362,9 @@ if __name__ == "__main__": ]) -""" -# doesnt work for some reason -print(verilog.convert(alu, ports=[in_a, in_a_stb, in_a_ack, - in_b, in_b_stb, in_b_ack, - out_z, out_z_stb, out_z_ack])) -""" + # works... but don't use, just do "python fname.py convert -t v" + #print (verilog.convert(alu, ports=[ + # alu.in_a, alu.in_a_stb, alu.in_a_ack, + # alu.in_b, alu.in_b_stb, alu.in_b_ack, + # alu.out_z, alu.out_z_stb, alu.out_z_ack, + # ])) -- 2.30.2