From a7346cf43bde2b63bd15f2a5ed540f9804eb291f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 12:52:20 +0000 Subject: [PATCH] --- openpower/sv/mv.vec.mdwn | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn index 0f035fb3f..28d6e8ec4 100644 --- a/openpower/sv/mv.vec.mdwn +++ b/openpower/sv/mv.vec.mdwn @@ -36,7 +36,15 @@ intended to cover: rd+2 = (rs >> 2 * 8) & (2^8 - 1) rd+3 = (rs >> 3 * 8) & (2^8 - 1) -and variants involving vec3 into 32 bit (4th byte set to zero) +and variants involving vec3 into 32 bit (4th byte set to zero). +TODO: include this pseudocode which shows how the vecN can do that. +in this example RA elwidth=32 and RB elwidth=8, RB is a vec4. + + for i in range(VL): + if predicate_bit_not_set(i) continue + uint8_t *start_point = (uint8_t*)(int_regfile[RA].i[i]) + for j in range(SUBVL): # vec4 + start_point[j] = some_op(int_regfile[RB].b[i*SUBVL + j]) ## Twin Predication, saturation, swizzle, and elwidth overrides -- 2.30.2