From a739e5f8465c5afec5ec4334809bd37d319d2680 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Mar 2018 04:39:49 +0000 Subject: [PATCH] cell mux naming convention (forgot to save, whoops) --- src/wire_def.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/wire_def.py b/src/wire_def.py index aca972b..dd4b384 100644 --- a/src/wire_def.py +++ b/src/wire_def.py @@ -1,9 +1,9 @@ # == Intermediate wire definitions ==# muxwire = ''' - Wire#(Bit#({1})) wrmux{0} <-mkDWire(0);''' + Wire#(Bit#({1})) wrcell{0}_mux <-mkDWire(0);''' generic_io = ''' - GenericIOType cell{0}_out=unpack(0); - Wire#(Bit#(1)) cell{0}_in <-mkDWire(0); + GenericIOType cell{0}_mux_out=unpack(0); + Wire#(Bit#(1)) cell{0}_mux_in <-mkDWire(0); ''' uartwires = ''' Wire#(Bit#(1)) wruart{0}_rx <-mkDWire(0); -- 2.30.2