From a74563c15831facf10fc10dd6f41d673684dd8aa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Sep 2022 14:18:46 +0100 Subject: [PATCH] mention ZOLC --- openpower/sv/rfc/ls001.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 97faa10af..35dbe1de3 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -87,9 +87,9 @@ to provide future expanded register file bitwidths and sizes. [^msr] # Hardware Implementations The fundamental principle of Simple-V is that it sits between Issue and -Decode, pausing the Program-Counter to service a "Sub-Program-Counter" -hardware for-loop. In practical terms for many first-version -implementations this is sufficient. +Decode, pausing the Program-Counter to service a "Sub-PC" +hardware for-loop. This is very similar to "Zero-Overhead Loops" +in High-end DSPs (TI MSP Series). **Considerable** effort has been expended to ensure that Simple-V is practical to implement on an extremely wide range of Industry-wide -- 2.30.2