From a75a9deff00afc2db17094e789db299ba2b39ed9 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Wed, 25 Mar 2020 19:43:24 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA
 and RISC-V

---
 2f/6facbbb20e6c8d4362d778d1d990a56a720f74 | 87 +++++++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 2f/6facbbb20e6c8d4362d778d1d990a56a720f74

diff --git a/2f/6facbbb20e6c8d4362d778d1d990a56a720f74 b/2f/6facbbb20e6c8d4362d778d1d990a56a720f74
new file mode 100644
index 0000000..ea30202
--- /dev/null
+++ b/2f/6facbbb20e6c8d4362d778d1d990a56a720f74
@@ -0,0 +1,87 @@
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+From: bugzilla-daemon@libre-riscv.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Wed, 25 Mar 2020 19:43:24 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
+X-Bugzilla-Flags: 
+X-Bugzilla-Changed-Fields: 
+Message-ID: <bug-186-13-dhxf6XiHJR@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
+References: <bug-186-13@http.bugs.libre-riscv.org/>
+X-Bugzilla-URL: http://bugs.libre-riscv.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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-- 
2.30.2