From a76aa88078164dc45028c7b673a71a16cf6c47ac Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 11 Mar 2020 07:36:49 +0000
Subject: [PATCH]

---
 3d_gpu/architecture/decoder.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/3d_gpu/architecture/decoder.mdwn b/3d_gpu/architecture/decoder.mdwn
index 737b14619..e049ec9be 100644
--- a/3d_gpu/architecture/decoder.mdwn
+++ b/3d_gpu/architecture/decoder.mdwn
@@ -1,5 +1,7 @@
 # Decoder
 
+<http://bugs.libre-riscv.org/show_bug.cgi?id=186>
+
 The decoder is in charge of translating the RISCV or POWER instruction stream into operations that can be handled by our backend. It will have an extra input bit, set via a MSR that will switch which architecture it treats an instruction as.
 
 Source code: <https://git.libre-riscv.org/?p=soc.git;a=tree;f=src/soc/decoder;hb=HEAD>
-- 
2.30.2