From a7785078b5edd903bf07686b3cdbc3c75a9bf58e Mon Sep 17 00:00:00 2001 From: Will Schmidt Date: Fri, 12 May 2017 15:35:17 +0000 Subject: [PATCH] rs6000.c (gimple-fold.h): New #include. [gcc] 2017-05-10 Will Schmidt * config/rs6000/rs6000.c (gimple-fold.h): New #include. (rs6000_gimple_fold_builtin): Add handling for early GIMPLE expansion of vector logical operations (and, andc, or, xor, nor, orc, nand) [gcc/testsuite] 2017-05-10 Will Schmidt * gcc.target/powerpc/fold-vec-logical-ands-char.c: New. * gcc.target/powerpc/fold-vec-logical-ands-int.c: New. * gcc.target/powerpc/fold-vec-logical-ands-longlong.c: New. * gcc.target/powerpc/fold-vec-logical-ands-short.c: New. * gcc.target/powerpc/fold-vec-logical-ors-char.c: New. * gcc.target/powerpc/fold-vec-logical-ors-int.c: New. * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: New. * gcc.target/powerpc/fold-vec-logical-ors-short.c: New. * gcc.target/powerpc/fold-vec-logical-other-char.c: New. * gcc.target/powerpc/fold-vec-logical-other-int.c: New. * gcc.target/powerpc/fold-vec-logical-other-longlong.c: New. * gcc.target/powerpc/fold-vec-logical-other-short.c: New. From-SVN: r247976 --- gcc/ChangeLog | 7 + gcc/config/rs6000/rs6000.c | 106 +++++++++++- gcc/testsuite/ChangeLog | 15 ++ .../powerpc/fold-vec-logical-ands-char.c | 108 ++++++++++++ .../powerpc/fold-vec-logical-ands-int.c | 108 ++++++++++++ .../powerpc/fold-vec-logical-ands-longlong.c | 107 ++++++++++++ .../powerpc/fold-vec-logical-ands-short.c | 107 ++++++++++++ .../powerpc/fold-vec-logical-ors-char.c | 126 ++++++++++++++ .../powerpc/fold-vec-logical-ors-int.c | 124 ++++++++++++++ .../powerpc/fold-vec-logical-ors-longlong.c | 161 ++++++++++++++++++ .../powerpc/fold-vec-logical-ors-short.c | 124 ++++++++++++++ .../powerpc/fold-vec-logical-other-char.c | 108 ++++++++++++ .../powerpc/fold-vec-logical-other-int.c | 108 ++++++++++++ .../powerpc/fold-vec-logical-other-longlong.c | 106 ++++++++++++ .../powerpc/fold-vec-logical-other-short.c | 108 ++++++++++++ 15 files changed, 1522 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-longlong.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 484263201d5..852630e3ee4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-05-10 Will Schmidt + + * config/rs6000/rs6000.c (gimple-fold.h): New #include. + (rs6000_gimple_fold_builtin): Add handling for early GIMPLE + expansion of vector logical operations (and, andc, or, xor, + nor, orc, nand). + 2017-05-12 Will Schmidt * gimple-fold.c (create_tmp_reg_or_ssa_name): Remove static declaration. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 267659bc520..2290439cfe3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -55,6 +55,7 @@ #include "reload.h" #include "sched-int.h" #include "gimplify.h" +#include "gimple-fold.h" #include "gimple-iterator.h" #include "gimple-ssa.h" #include "gimple-walk.h" @@ -17204,7 +17205,110 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } - + /* Flavors of vec_and. */ + case ALTIVEC_BUILTIN_VAND: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vec_andc. */ + case ALTIVEC_BUILTIN_VANDC: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + gimple *g = gimple_build_assign(temp, BIT_NOT_EXPR, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before(gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vec_nand. */ + case P8V_BUILTIN_VEC_NAND: + case P8V_BUILTIN_NAND_V16QI: + case P8V_BUILTIN_NAND_V8HI: + case P8V_BUILTIN_NAND_V4SI: + case P8V_BUILTIN_NAND_V4SF: + case P8V_BUILTIN_NAND_V2DF: + case P8V_BUILTIN_NAND_V2DI: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + gimple *g = gimple_build_assign(temp, BIT_AND_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before(gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vec_or. */ + case ALTIVEC_BUILTIN_VOR: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* flavors of vec_orc. */ + case P8V_BUILTIN_ORC_V16QI: + case P8V_BUILTIN_ORC_V8HI: + case P8V_BUILTIN_ORC_V4SI: + case P8V_BUILTIN_ORC_V4SF: + case P8V_BUILTIN_ORC_V2DF: + case P8V_BUILTIN_ORC_V2DI: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + gimple *g = gimple_build_assign(temp, BIT_NOT_EXPR, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before(gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vec_xor. */ + case ALTIVEC_BUILTIN_VXOR: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vec_nor. */ + case ALTIVEC_BUILTIN_VNOR: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + gimple *g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before(gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } default: break; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4b9297b6c65..1bffa4a82ba 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,18 @@ +2017-05-12 Will Schmidt + + * gcc.target/powerpc/fold-vec-logical-ands-char.c: New. + * gcc.target/powerpc/fold-vec-logical-ands-int.c: New. + * gcc.target/powerpc/fold-vec-logical-ands-longlong.c: New. + * gcc.target/powerpc/fold-vec-logical-ands-short.c: New. + * gcc.target/powerpc/fold-vec-logical-ors-char.c: New. + * gcc.target/powerpc/fold-vec-logical-ors-int.c: New. + * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: New. + * gcc.target/powerpc/fold-vec-logical-ors-short.c: New. + * gcc.target/powerpc/fold-vec-logical-other-char.c: New. + * gcc.target/powerpc/fold-vec-logical-other-int.c: New. + * gcc.target/powerpc/fold-vec-logical-other-longlong.c: New. + * gcc.target/powerpc/fold-vec-logical-other-short.c: New. + 2017-05-12 Paolo Carlini PR c++/49604 diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c new file mode 100644 index 00000000000..021da58441e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-char.c @@ -0,0 +1,108 @@ +/* Verify that overloaded built-ins for vec_and and vec_andc + * with char inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -O1" } */ + +#include + +vector signed char +test1_and (vector bool char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed char +test1_andc (vector bool char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed char +test2_and (vector signed char x, vector bool char y) +{ + vector signed char *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed char +test2_andc (vector signed char x, vector bool char y) +{ + vector signed char *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed char +test3_and (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed char +test3_andc (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned char +test4_and (vector bool char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned char +test4_andc (vector bool char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned char +test5_and (vector unsigned char x, vector bool char y) +{ + vector unsigned char *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned char +test5_andc (vector unsigned char x, vector bool char y) +{ + vector unsigned char *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned char +test6_and (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned char +test6_andc (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_andc (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxland\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c new file mode 100644 index 00000000000..ccac7d5f8f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-int.c @@ -0,0 +1,108 @@ +/* Verify that overloaded built-ins for vec_and, vec_andc, vec_or and vec_xor + * with int inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O1" } */ + +#include + +vector signed int +test1_and (vector bool int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed int +test1_andc (vector bool int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed int +test2_and (vector signed int x, vector bool int y) +{ + vector signed int *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed int +test2_andc (vector signed int x, vector bool int y) +{ + vector signed int *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed int +test3_and (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed int +test3_andc (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned int +test4_and (vector bool int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned int +test4_andc (vector bool int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned int +test5_and (vector unsigned int x, vector bool int y) +{ + vector unsigned int *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned int +test5_andc (vector unsigned int x, vector bool int y) +{ + vector unsigned int *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned int +test6_and (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned int +test6_andc (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_andc (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxland\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-longlong.c new file mode 100644 index 00000000000..76bece11a99 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-longlong.c @@ -0,0 +1,107 @@ +/* Verify that overloaded built-ins for vec_and,vec_or,vec_xor with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector signed long long +test1_and (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed long long +test1_andc (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed long long +test2_and (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed long long +test2_andc (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed long long +test3_and (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed long long +test3_andc (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned long long +test4_and (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned long long +test4_andc (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned long long +test5_and (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned long long +test5_andc (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned long long +test6_and (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned long long +test6_andc (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_andc (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxland\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c new file mode 100644 index 00000000000..8ee320675b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ands-short.c @@ -0,0 +1,107 @@ +/* Verify that overloaded built-ins for vec_and,vec_or,vec_xor with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O1" } */ + +#include + +vector signed short +test1_and (vector bool short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed short +test1_andc (vector bool short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed short +test2_and (vector signed short x, vector bool short y) +{ + vector signed short *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed short +test2_andc (vector signed short x, vector bool short y) +{ + vector signed short *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector signed short +test3_and (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector signed short +test3_andc (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned short +test4_and (vector bool short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned short +test4_andc (vector bool short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned short +test5_and (vector unsigned short x, vector bool short y) +{ + vector unsigned short *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned short +test5_andc (vector unsigned short x, vector bool short y) +{ + vector unsigned short *foo; + *foo += vec_andc (x, y); + return *foo; +} + +vector unsigned short +test6_and (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_and (x, y); + return *foo; +} + +vector unsigned short +test6_andc (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_andc (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxland\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlandc\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c new file mode 100644 index 00000000000..283189f8713 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-char.c @@ -0,0 +1,126 @@ +/* Verify that overloaded built-ins for vec_or, vec_xor, vec_nor + * with char inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -O1" } */ + +#include + + +vector signed char +test1_or (vector bool char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed char +test1_xor (vector bool char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed char +test2_or (vector signed char x, vector bool char y) +{ + vector signed char *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed char +test2_xor (vector signed char x, vector bool char y) +{ + vector signed char *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed char +test3_or (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed char +test3_xor (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed char +test3_nor (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_nor (x, y); + return *foo; +} + + +vector unsigned char +test4_or (vector bool char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned char +test4_xor (vector bool char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned char +test5_or (vector unsigned char x, vector bool char y) +{ + vector unsigned char *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned char +test5_xor (vector unsigned char x, vector bool char y) +{ + vector unsigned char *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned char +test6_or (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned char +test6_xor (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned char +test6_nor (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_nor (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c new file mode 100644 index 00000000000..11e98ae4dcf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-int.c @@ -0,0 +1,124 @@ +/* Verify that overloaded built-ins for vec_and, vec_andc, vec_or and vec_xor + * with int inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O1" } */ + +#include + +vector signed int +test1_or (vector bool int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed int +test1_xor (vector bool int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed int +test2_or (vector signed int x, vector bool int y) +{ + vector signed int *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed int +test2_xor (vector signed int x, vector bool int y) +{ + vector signed int *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed int +test3_or (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed int +test3_xor (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed int +test3_nor (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector unsigned int +test4_or (vector bool int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned int +test4_xor (vector bool int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned int +test5_or (vector unsigned int x, vector bool int y) +{ + vector unsigned int *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned int +test5_xor (vector unsigned int x, vector bool int y) +{ + vector unsigned int *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned int +test6_or (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned int +test6_xor (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned int +test6_nor (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_nor (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c new file mode 100644 index 00000000000..ac532f52d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c @@ -0,0 +1,161 @@ +/* Verify that overloaded built-ins for vec_or, vec_xor, vec_nor with + * long long inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector signed long long +test1_or (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed long long +test1_xor (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed long long +test1_nor (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector signed long long +test2_or (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed long long +test2_xor (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed long long +test2_nor (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector signed long long +test3_or (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed long long +test3_xor (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed long long +test3_nor (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector unsigned long long +test4_or (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned long long +test4_xor (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned long long +test4_nor (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector unsigned long long +test5_or (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned long long +test5_xor (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned long long +test5_nor (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector unsigned long long +test6_or (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned long long +test6_xor (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned long long +test6_nor (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_nor (x, y); + return *foo; +} + +// Codegen on power7 is such that the vec_or() tests generate more xxlor +// instructions than what is seen on power8 or newer. +// Thus, an additional target close for the xxlor instruction check. +/* { dg-final { scan-assembler-times {\mxxlor\M} 6 { target p8vector_hw } } } */ +/* { dg-final { scan-assembler-times {\mxxlor\M} 24 { target { ! p8vector_hw } } } } */ + +/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c new file mode 100644 index 00000000000..24f3a55efe0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-short.c @@ -0,0 +1,124 @@ +/* Verify that overloaded built-ins for vec_or, vec_xor, vec_nor with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O1" } */ + +#include + +vector signed short +test1_or (vector bool short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed short +test1_xor (vector bool short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed short +test2_or (vector signed short x, vector bool short y) +{ + vector signed short *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed short +test2_xor (vector signed short x, vector bool short y) +{ + vector signed short *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed short +test3_or (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector signed short +test3_xor (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector signed short +test3_nor (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_nor (x, y); + return *foo; +} + +vector unsigned short +test4_or (vector bool short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned short +test4_xor (vector bool short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned short +test5_or (vector unsigned short x, vector bool short y) +{ + vector unsigned short *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned short +test5_xor (vector unsigned short x, vector bool short y) +{ + vector unsigned short *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned short +test6_or (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_or (x, y); + return *foo; +} + +vector unsigned short +test6_xor (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_xor (x, y); + return *foo; +} + +vector unsigned short +test6_nor (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_nor (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlnor\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c new file mode 100644 index 00000000000..8726df617de --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c @@ -0,0 +1,108 @@ +/* Verify that overloaded built-ins for vec_orc and vec_nand with char + * inputs produce the right results. These intrinsics (vec_orc, + * vec_nand) were added as part of ISA 2.07 (P8). */ + +/* { dg-do compile } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mpower8-vector -O1" } */ + +#include + +vector signed char +test1_orc (vector bool char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed char +test1_nand (vector bool char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed char +test2_orc (vector signed char x, vector bool char y) +{ + vector signed char *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed char +test2_nand (vector signed char x, vector bool char y) +{ + vector signed char *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed char +test3_orc (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed char +test3_nand (vector signed char x, vector signed char y) +{ + vector signed char *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned char +test4_orc (vector bool char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned char +test4_nand (vector bool char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned char +test5_orc (vector unsigned char x, vector bool char y) +{ + vector unsigned char *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned char +test5_nand (vector unsigned char x, vector bool char y) +{ + vector unsigned char *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned char +test6_orc (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned char +test6_nand (vector unsigned char x, vector unsigned char y) +{ + vector unsigned char *foo; + *foo += vec_nand (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlnand\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c new file mode 100644 index 00000000000..61d34059b67 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c @@ -0,0 +1,108 @@ +/* Verify that overloaded built-ins for vec_orc and vec_nand with int + * inputs produce the right results. These intrinsics (vec_orc, + * vec_nand) were added as part of ISA 2.07 (P8). */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O1" } */ + +#include + +vector signed int +test1_orc (vector bool int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed int +test1_nand (vector bool int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed int +test2_orc (vector signed int x, vector bool int y) +{ + vector signed int *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed int +test2_nand (vector signed int x, vector bool int y) +{ + vector signed int *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed int +test3_orc (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed int +test3_nand (vector signed int x, vector signed int y) +{ + vector signed int *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned int +test4_orc (vector bool int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned int +test4_nand (vector bool int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned int +test5_orc (vector unsigned int x, vector bool int y) +{ + vector unsigned int *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned int +test5_nand (vector unsigned int x, vector bool int y) +{ + vector unsigned int *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned int +test6_orc (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned int +test6_nand (vector unsigned int x, vector unsigned int y) +{ + vector unsigned int *foo; + *foo += vec_nand (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlnand\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c new file mode 100644 index 00000000000..8e14927620e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c @@ -0,0 +1,106 @@ +/* Verify that overloaded built-ins for vec_orc and vec_nand with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O1" } */ + +#include + +vector signed long long +test1_orc (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed long long +test1_nand (vector bool long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed long long +test2_orc (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed long long +test2_nand (vector signed long long x, vector bool long long y) +{ + vector signed long long *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed long long +test3_orc (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed long long +test3_nand (vector signed long long x, vector signed long long y) +{ + vector signed long long *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned long long +test4_orc (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned long long +test4_nand (vector bool long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned long long +test5_orc (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned long long +test5_nand (vector unsigned long long x, vector bool long long y) +{ + vector unsigned long long *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned long long +test6_orc (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_orc (x, y); + return *foo; +} +vector unsigned long long +test6_nand (vector unsigned long long x, vector unsigned long long y) +{ + vector unsigned long long *foo; + *foo += vec_nand (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlorc\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlnand\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c new file mode 100644 index 00000000000..cc354b935dc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c @@ -0,0 +1,108 @@ +/* Verify that overloaded built-ins for vec_orc and vec_nand with short + * inputs produce the right results. These intrinsics (vec_orc, + * vec_nand) were added as part of ISA 2.07 (P8). */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O1" } */ + +#include + +vector signed short +test1_orc (vector bool short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed short +test1_nand (vector bool short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed short +test2_orc (vector signed short x, vector bool short y) +{ + vector signed short *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed short +test2_nand (vector signed short x, vector bool short y) +{ + vector signed short *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector signed short +test3_orc (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector signed short +test3_nand (vector signed short x, vector signed short y) +{ + vector signed short *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned short +test4_orc (vector bool short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned short +test4_nand (vector bool short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned short +test5_orc (vector unsigned short x, vector bool short y) +{ + vector unsigned short *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned short +test5_nand (vector unsigned short x, vector bool short y) +{ + vector unsigned short *foo; + *foo += vec_nand (x, y); + return *foo; +} + +vector unsigned short +test6_orc (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_orc (x, y); + return *foo; +} + +vector unsigned short +test6_nand (vector unsigned short x, vector unsigned short y) +{ + vector unsigned short *foo; + *foo += vec_nand (x, y); + return *foo; +} + +/* { dg-final { scan-assembler-times {\mxxlnand\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxlorc\M} 6 } } */ -- 2.30.2