From a780a4b12a2ff6a59d809eee841b3237a5875181 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 2 Mar 2022 13:56:55 +0000
Subject: [PATCH] invert reset and chip-select on dram, and initialise uart
 input in iverilog sim

---
 src/simsoctb.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/simsoctb.v b/src/simsoctb.v
index f51ed07..3ba4c91 100644
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -47,11 +47,11 @@ module simsoctb;
   ddr3 #(
     .check_strict_timing(0)
   ) ram_chip (
-    .rst_n(dram_rst),
+    .rst_n(~dram_rst),
     .ck(dram_ck),
     .ck_n(~dram_ck),
     .cke(dram_cke),
-    .cs_n(dram_cs_n),
+    .cs_n(~dram_cs_n),
     .ras_n(dram_ras_n),
     .cas_n(dram_cas_n),
     .we_n(dram_we_n),
@@ -69,7 +69,7 @@ module simsoctb;
 
   // uart, LEDs, switches
   wire uart_tx ;
-  wire uart_rx;
+  reg uart_rx = 0;
   wire led_0;
   wire led_1;
   wire led_2;
-- 
2.30.2