From a7ac1f38306ef3d22926425cca2970cc1ac1bd10 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 20 Dec 2021 13:42:09 +0000 Subject: [PATCH] more code-comments --- src/soc/experiment/mmu.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index adef05ff..f139e85a 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -539,12 +539,14 @@ class MMU(Elaboratable): sync += Display(" RADIX_FINISH") comb += v.state.eq(State.IDLE) + # check and report either error or done. with m.If((v.state == State.RADIX_FINISH) | ((v.state == State.RADIX_LOAD_TLB) & r.iside)): comb += v.err.eq(v.invalid | v.badtree | v.segerror | v.perm_err | v.rc_error) comb += v.done.eq(~v.err) + # PID is only valid if MSB of address is zero with m.If(~r.addr[63]): comb += effpid.eq(r.pid) -- 2.30.2