From a7c9f8c59c0d8ed1f44be02c1541a5a50f866172 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 19 May 2022 17:09:55 +0100 Subject: [PATCH] --- openpower/sv/bitmanip.mdwn | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index b6f53bb00..04c671e55 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -97,7 +97,7 @@ TODO: convert all instructions to use RT and not RS | NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | TLI-Form | | NN | RT | RA | RB | RC | nh 00 00 |1 | binlut | VA-Form | | NN | RT | RA | RB | /BFA/ | 0 01 00 |1 | bincrflut | VA-Form | -| NN | | | | | 1 01 00 |1 | rsvd | | +| NN | RT | RA | RB | RC | 1 01 00 |1 | grevlogr | VA-Form | | NN | | | | | - 10 00 |1 | rsvd | | | NN | | | | | 0 11 00 |1 | svshape | SVM-Form | | NN | | | | | 1 11 00 |1 | svremap | SVRM-Form | @@ -456,7 +456,7 @@ set to the required length: The following settings provide the required mask constants: -| RA | RB | imm | iv | result | +| RA=0 | RB | imm | iv | result | | ------- | ------- | ---------- | -- | ---------- | | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... | | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... | @@ -499,6 +499,24 @@ uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b) if (shamt & step) x = dorow(imm, x, step, is32b) return x; } +``` + +A 3-register variant may specify different LUT-pairs per row, +using one byte of RC for each. + +``` +uint64_t grevlutr(uint64_t RA, uint64_t RB, uint64_t RC, bool iv, bool is32b) +{ + uint64_t x = 0x5555_5555_5555_5555; + if (RA != 0) x = GPR(RA); + if (iv) x = ~x; + int shamt = RB & 31 if is32b else 63 + for i in 0 to (6-is32b) + step = 1<>(i*8))&0xff + if (shamt & step) x = dorow(imm, x, step, is32b) + return x; +} ``` -- 2.30.2