From a7f9d13ba7658db36aef5fcfa3c72e01c6b5c108 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 2 Sep 2020 15:13:06 +0100 Subject: [PATCH] add cmpl regression test (one binary, one assembly) --- src/soc/fu/alu/test/test_pipe_caller.py | 27 +++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index f03ef971..5d8122c7 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -238,8 +238,8 @@ class ALUTestCase(TestAccumulatorBase): lst = ["cmpl 6, 0, 17, 10"] initial_regs = [0] * 32 - initial_regs[0x11] = 0xffff6dc1 - initial_regs[0xa] = 0 + initial_regs[0x11] = 0x1c026 + initial_regs[0xa] = 0xFEDF3FFF0001C025 XER = 0xe00c0000 CR = 0x35055050 @@ -247,6 +247,29 @@ class ALUTestCase(TestAccumulatorBase): initial_sprs = {'XER': XER}, initial_cr = CR) + def case_cmpl_microwatt_0_disasm(self): + """microwatt 1.bin: disassembled version + 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10 + register_file.vhdl: Reading GPR 11 000000000001C026 + register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025 + cr_file.vhdl: Reading CR 35055050 + cr_file.vhdl: Writing 35055058 to CR mask 01 35055058 + """ + + dis = ["cmpl 6, 0, 17, 10"] + lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040 + initial_regs = [0] * 32 + initial_regs[0x11] = 0x1c026 + initial_regs[0xa] = 0xFEDF3FFF0001C025 + XER = 0xe00c0000 + CR = 0x35055050 + + p = Program(lst, bigendian) + p.assembly = '\n'.join(dis)+'\n' + self.add_case(p, initial_regs, + initial_sprs = {'XER': XER}, + initial_cr = CR) + def case_cmplw_microwatt_1(self): """microwatt 1.bin: 10d94: 40 20 96 7c cmplw cr1,r22,r4 -- 2.30.2