From a807caee952002ce79cb04f073911c0e28cc193e Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 26 Sep 2023 11:56:23 +0100
Subject: [PATCH] Added english language description, spaces and brackets for
 ldu instruction

---
 openpower/isa/fixedload.mdwn | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index a87d6332..2ff1a3b0 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -542,6 +542,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA)+ (DS||0b00). The doubleword in storage
+    addressed by EA is loaded into RT.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
-- 
2.30.2