From a8105959bdd74007458c528e053dcf22c245474b Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Fri, 8 May 2015 12:00:10 +0000 Subject: [PATCH] [AArch64] Idiomatic 64x1 comparisons in arm_neon.h gcc/: * config/aarch64/arm_neon.h (vceq_s64, vceq_u64, vceqz_s64, vceqz_u64, vcge_s64, vcge_u64, vcgez_s64, vcgt_s64, vcgt_u64, vcgtz_s64, vcle_s64, vcle_u64, vclez_s64, vclt_s64, vclt_u64, vcltz_s64, vtst_s64, vtst_u64): Rewrite using gcc vector extensions. gcc/testsuite/: * gcc.target/aarch64/singleton_intrinsics_1.c: Generalize regex to allow cmlt or sshr. From-SVN: r222909 --- gcc/ChangeLog | 7 ++++ gcc/config/aarch64/arm_neon.h | 36 +++++++++---------- gcc/testsuite/ChangeLog | 5 +++ .../aarch64/singleton_intrinsics_1.c | 4 +-- 4 files changed, 32 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 87a75d1398e..6f4558fad8a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-05-08 Alan Lawrence + + * config/aarch64/arm_neon.h (vceq_s64, vceq_u64, vceqz_s64, vceqz_u64, + vcge_s64, vcge_u64, vcgez_s64, vcgt_s64, vcgt_u64, vcgtz_s64, vcle_s64, + vcle_u64, vclez_s64, vclt_s64, vclt_u64, vcltz_s64, vtst_s64, + vtst_u64): Rewrite using gcc vector extensions. + 2015-05-08 Alan Lawrence * config/aarch64/aarch64-simd.md (aarch64_vcond_internal, diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index e9cc82577a9..9896e8c21af 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -11619,7 +11619,7 @@ vceq_s32 (int32x2_t __a, int32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_s64 (int64x1_t __a, int64x1_t __b) { - return (uint64x1_t) {__a[0] == __b[0] ? -1ll : 0ll}; + return (uint64x1_t) (__a == __b); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -11643,7 +11643,7 @@ vceq_u32 (uint32x2_t __a, uint32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) {__a[0] == __b[0] ? -1ll : 0ll}; + return (__a == __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -11779,7 +11779,7 @@ vceqz_s32 (int32x2_t __a) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceqz_s64 (int64x1_t __a) { - return (uint64x1_t) {__a[0] == 0ll ? -1ll : 0ll}; + return (uint64x1_t) (__a == __AARCH64_INT64_C (0)); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -11803,7 +11803,7 @@ vceqz_u32 (uint32x2_t __a) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceqz_u64 (uint64x1_t __a) { - return (uint64x1_t) {__a[0] == 0ll ? -1ll : 0ll}; + return (__a == __AARCH64_UINT64_C (0)); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -11933,7 +11933,7 @@ vcge_s32 (int32x2_t __a, int32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_s64 (int64x1_t __a, int64x1_t __b) { - return (uint64x1_t) {__a[0] >= __b[0] ? -1ll : 0ll}; + return (uint64x1_t) (__a >= __b); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -11957,7 +11957,7 @@ vcge_u32 (uint32x2_t __a, uint32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) {__a[0] >= __b[0] ? -1ll : 0ll}; + return (__a >= __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12081,7 +12081,7 @@ vcgez_s32 (int32x2_t __a) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgez_s64 (int64x1_t __a) { - return (uint64x1_t) {__a[0] >= 0ll ? -1ll : 0ll}; + return (uint64x1_t) (__a >= __AARCH64_INT64_C (0)); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12175,7 +12175,7 @@ vcgt_s32 (int32x2_t __a, int32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_s64 (int64x1_t __a, int64x1_t __b) { - return (uint64x1_t) (__a[0] > __b[0] ? -1ll : 0ll); + return (uint64x1_t) (__a > __b); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -12199,7 +12199,7 @@ vcgt_u32 (uint32x2_t __a, uint32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) (__a[0] > __b[0] ? -1ll : 0ll); + return (__a > __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12323,7 +12323,7 @@ vcgtz_s32 (int32x2_t __a) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgtz_s64 (int64x1_t __a) { - return (uint64x1_t) {__a[0] > 0ll ? -1ll : 0ll}; + return (uint64x1_t) (__a > __AARCH64_INT64_C (0)); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12417,7 +12417,7 @@ vcle_s32 (int32x2_t __a, int32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_s64 (int64x1_t __a, int64x1_t __b) { - return (uint64x1_t) {__a[0] <= __b[0] ? -1ll : 0ll}; + return (uint64x1_t) (__a <= __b); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -12441,7 +12441,7 @@ vcle_u32 (uint32x2_t __a, uint32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) {__a[0] <= __b[0] ? -1ll : 0ll}; + return (__a <= __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12565,7 +12565,7 @@ vclez_s32 (int32x2_t __a) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclez_s64 (int64x1_t __a) { - return (uint64x1_t) {__a[0] <= 0ll ? -1ll : 0ll}; + return (uint64x1_t) (__a <= __AARCH64_INT64_C (0)); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12659,7 +12659,7 @@ vclt_s32 (int32x2_t __a, int32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_s64 (int64x1_t __a, int64x1_t __b) { - return (uint64x1_t) {__a[0] < __b[0] ? -1ll : 0ll}; + return (uint64x1_t) (__a < __b); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -12683,7 +12683,7 @@ vclt_u32 (uint32x2_t __a, uint32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) {__a[0] < __b[0] ? -1ll : 0ll}; + return (__a < __b); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -12807,7 +12807,7 @@ vcltz_s32 (int32x2_t __a) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcltz_s64 (int64x1_t __a) { - return (uint64x1_t) {__a[0] < 0ll ? -1ll : 0ll}; + return (uint64x1_t) (__a < __AARCH64_INT64_C (0)); } __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) @@ -23767,7 +23767,7 @@ vtst_s32 (int32x2_t __a, int32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_s64 (int64x1_t __a, int64x1_t __b) { - return (uint64x1_t) {(__a[0] & __b[0]) ? -1ll : 0ll}; + return (uint64x1_t) ((__a & __b) != __AARCH64_INT64_C (0)); } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) @@ -23791,7 +23791,7 @@ vtst_u32 (uint32x2_t __a, uint32x2_t __b) __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_u64 (uint64x1_t __a, uint64x1_t __b) { - return (uint64x1_t) {(__a[0] & __b[0]) ? -1ll : 0ll}; + return ((__a & __b) != __AARCH64_UINT64_C (0)); } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 79b2aa262f2..e71b8e043d7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-05-08 Alan Lawrence + + * gcc.target/aarch64/singleton_intrinsics_1.c: Generalize regex to + allow cmlt or sshr. + 2015-05-08 Marek Polacek PR c/64918 diff --git a/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c b/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c index 4a0934b01f9..633a0d24ead 100644 --- a/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c +++ b/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c @@ -235,8 +235,8 @@ test_vrshl_u64 (uint64x1_t a, int64x1_t b) return vrshl_u64 (a, b); } -/* For int64x1_t, sshr...#63 is output instead of the equivalent cmlt...#0. */ -/* { dg-final { scan-assembler-times "\\tsshr\\td\[0-9\]+" 2 } } */ +/* For int64x1_t, sshr...#63 is equivalent to cmlt...#0. */ +/* { dg-final { scan-assembler-times "\\t(?:sshr|cmlt)\\td\[0-9\]+" 2 } } */ int64x1_t test_vshr_n_s64 (int64x1_t a) -- 2.30.2