From a814f3d8a7d2e87ed357cd600408012f13c6a90d Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 27 Nov 2019 16:49:53 +0000 Subject: [PATCH] ac/llvm: improve sync scope for global atomics Stronger ordering is implemented in SPIRV->NIR with barriers. Signed-off-by: Rhys Perry Reviewed-by: Samuel Pitoiset --- src/amd/llvm/ac_nir_to_llvm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index ddf9f09fe0c..830866bc5cb 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3024,6 +3024,9 @@ static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx, nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr); if (deref->mode == nir_var_mem_global) { + /* use "singlethread" sync scope to implement relaxed ordering */ + sync_scope = LLVM_VERSION_MAJOR >= 9 ? "singlethread-one-as" : "singlethread"; + LLVMTypeRef ptr_type = LLVMPointerType(LLVMTypeOf(src), LLVMGetPointerAddressSpace(LLVMTypeOf(ptr))); ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ptr_type , ""); } -- 2.30.2