From a8200a773fb8cf2ce2d8793716b62e01c97dd731 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 18 Jun 2016 14:13:36 +0200
Subject: [PATCH] A few modifications after pull request comments

- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
---
 frontends/ast/ast.cc | 4 ++--
 kernel/rtlil.cc      | 2 +-
 kernel/rtlil.h       | 3 +--
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index ba02dd4c5..57de725d8 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -997,7 +997,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			for (auto n : global_decls)
 				(*it)->children.push_back(n->clone());
 
-			for (auto n : design->packages){
+			for (auto n : design->verilog_packages){
 				for (auto o : n->children) {
 					AstNode *cloned_node = o->clone();
 					cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
@@ -1023,7 +1023,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			design->add(process_module(*it, defer));
 		}
 		else if ((*it)->type == AST_PACKAGE){
-			design->packages.push_back((*it)->clone());
+			design->verilog_packages.push_back((*it)->clone());
 		}
 		else
 			global_decls.push_back(*it);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9e09d9f04..9da6d2816 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -304,7 +304,7 @@ RTLIL::Design::~Design()
 {
 	for (auto it = modules_.begin(); it != modules_.end(); ++it)
 		delete it->second;
-	for (auto n : packages)
+	for (auto n : verilog_packages)
 		delete n;
 }
 
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 275ba6820..274f97023 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -18,7 +18,6 @@
  */
 
 #include "kernel/yosys.h"
-#include "frontends/ast/ast.h"
 
 #ifndef RTLIL_H
 #define RTLIL_H
@@ -793,7 +792,7 @@ struct RTLIL::Design
 
 	int refcount_modules_;
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
-	std::vector<AST::AstNode*> packages;
+	std::vector<AST::AstNode*> verilog_packages;
 
 	std::vector<RTLIL::Selection> selection_stack;
 	dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
-- 
2.30.2