From a86b89389e3a62ce131ffe8481b92ac3edf7e41b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 24 Nov 2018 01:34:30 +0000 Subject: [PATCH] tidyup --- cpu_decoder.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu_decoder.py b/cpu_decoder.py index 3f91824..995a04c 100644 --- a/cpu_decoder.py +++ b/cpu_decoder.py @@ -186,14 +186,14 @@ class CPUDecoder(Module): # fence c[F3.fence] = \ If((self.immediate[8:12] == immz) & (self.rs1 == regz) & \ - (self.rd == regz), + (self.rd == regz), self.decode_action.eq(DA.fence) ).Else( self.decode_action.eq(DA.trap_illegal_instruction)) # fence.i c[F3.fence_i] = \ If((self.immediate[0:12] == immz) & (self.rs1 == regz) & \ - (self.rd == regz), + (self.rd == regz), self.decode_action.eq(DA.fence_i) ).Else( self.decode_action.eq(DA.trap_illegal_instruction)) @@ -210,11 +210,11 @@ class CPUDecoder(Module): regz = Constant(0, 5) # ebreak c[F3.ecall_ebreak] = \ - If((self.immediate != ~b1) | (self.rs1 != regz) | \ - (self.rd != regz), - self.decode_action.eq(DA.trap_illegal_instruction) + If((self.immediate == ~b1) ^ (self.rs1 == regz) & \ + (self.rd == regz), + self.decode_action.eq(DA.trap_ecall_ebreak) ).Else( - self.decode_action.eq(DA.trap_ecall_ebreak)) + self.decode_action.eq(DA.trap_illegal_instruction)) # csrs for op in [ F3.csrrw, F3.csrrs, F3.csrrc, F3.csrrwi, F3.csrrsi, F3.csrrci]: -- 2.30.2