From a876c5dd61a53230de74b2ca2900e0e09490da95 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 11:04:27 +0000 Subject: [PATCH] add dummy pll to experiments10_verilog --- experiments10_verilog/Makefile | 1 + experiments10_verilog/add.py | 81 ++++++++++++++++++++++++++++--- experiments10_verilog/doDesign.py | 8 ++- 3 files changed, 81 insertions(+), 9 deletions(-) diff --git a/experiments10_verilog/Makefile b/experiments10_verilog/Makefile index 9dcb45f..1a5e346 100755 --- a/experiments10_verilog/Makefile +++ b/experiments10_verilog/Makefile @@ -3,6 +3,7 @@ PHYSICAL_SYNTHESIS = Coriolis DESIGN_KIT = cmos45 YOSYS_FLATTEN = No + YOSYS_BLACKBOXES = pll CHIP = chip CORE = add USE_CLOCKTREE = Yes diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py index 3e66b26..909607a 100644 --- a/experiments10_verilog/add.py +++ b/experiments10_verilog/add.py @@ -1,7 +1,8 @@ # generate add.il ilang file with: python3 add.py # -from nmigen import Elaboratable, Signal, Module, Const, DomainRenamer +from nmigen import (Elaboratable, Signal, Module, Const, DomainRenamer, + ClockSignal, ResetSignal) from nmigen.cli import verilog # to get c4m-jtag @@ -12,9 +13,10 @@ from nmigen.cli import verilog from c4m.nmigen.jtag.tap import TAP, IOType from nmigen_soc.wishbone.sram import SRAM from nmigen import Memory +from dummypll import DummyPLL -class ADD(Elaboratable): +class Core(Elaboratable): def __init__(self, width): self.width = width self.a = Signal(width) @@ -39,7 +41,7 @@ class ADD(Elaboratable): self.memsizes = [] #self.memsizes.append((32, 32)) # width, depth self.memsizes.append((32, 16)) # width, depth - self.memsizes.append((32, 16)) # width, depth + #self.memsizes.append((32, 16)) # width, depth # create and connect wishbone(s). okok, a better solution is to # use a Wishbone Arbiter, and only have one WB bus. @@ -78,6 +80,7 @@ class ADD(Elaboratable): def elaborate(self, platform): m = Module() + # create JTAG module m.submodules.jtag = jtag = self.jtag m.d.comb += self.sr.i.eq(self.sr.o) # loopback test @@ -136,6 +139,68 @@ class ADD(Elaboratable): return m +class ADD(Elaboratable): + def __init__(self, width): + self.width = width + self.a = Signal(width) + self.b = Signal(width) + self.f = Signal(width) + self.jtag_tck = Signal(reset_less=True) + self.jtag_tms = Signal(reset_less=True) + self.jtag_tdi = Signal(reset_less=True) + self.jtag_tdo = Signal(reset_less=True) + + # PLL input mode and test signals + self.a0 = Signal() + self.a1 = Signal() + self.pll_vco = Signal() + self.pll_test = Signal() + + # QTY 1, dummy PLL + self.dummypll = DummyPLL(instance=True) + + # core + self.core = Core(width) + + def elaborate(self, platform): + m = Module() + + # create PLL module + m.submodules.wrappll = pll = self.dummypll + + # connect up PLL + sys_clk = ClockSignal() + m.d.comb += pll.clk_24_i.eq(sys_clk) + m.d.comb += pll.clk_sel_i[0].eq(self.a0) + m.d.comb += pll.clk_sel_i[1].eq(self.a1) + m.d.comb += self.pll_vco.eq(pll.pll_vco_o) + m.d.comb += self.pll_test.eq(pll.pll_test_o) + + # create core module + dr = DomainRenamer("coresync") + m.submodules.core = core = dr(self.core) + + # connect reset + sys_rst = ResetSignal() + core_rst = ResetSignal("coresync") + m.d.comb += core_rst.eq(sys_rst) + + # connect core from PLL + core_clk = ClockSignal("coresync") + m.d.comb += core_clk.eq(pll.clk_pll_o) + + # and now the internal signals to the core + m.d.comb += core.a.eq(self.a) + m.d.comb += core.b.eq(self.b) + m.d.comb += self.f.eq(core.f) + + # and to JTAG + m.d.comb += self.jtag_tdo.eq(self.core.jtag.bus.tdo) + m.d.comb += self.core.jtag.bus.tdi.eq(self.jtag_tdi) + m.d.comb += self.core.jtag.bus.tms.eq(self.jtag_tms) + m.d.comb += self.core.jtag.bus.tck.eq(self.jtag_tck) + return m + def create_verilog(dut, ports, test_name): vl = verilog.convert(dut, name=test_name, ports=ports) @@ -145,7 +210,9 @@ def create_verilog(dut, ports, test_name): if __name__ == "__main__": alu = DomainRenamer("sys")(ADD(width=4)) create_verilog(alu, [alu.a, alu.b, alu.f, - alu.jtag.bus.tck, - alu.jtag.bus.tms, - alu.jtag.bus.tdo, - alu.jtag.bus.tdi], "add") + alu.a0, alu.a1, # PLL mode + alu.pll_test, alu.pll_vco, # PLL test + alu.jtag_tck, + alu.jtag_tms, + alu.jtag_tdo, + alu.jtag_tdi], "add") diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py index f79a3cc..f7ee17d 100644 --- a/experiments10_verilog/doDesign.py +++ b/experiments10_verilog/doDesign.py @@ -44,6 +44,7 @@ def scriptMain ( **kw ): , (IoPin.SOUTH, None, 'power_0' , 'vdd' ) , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' ) , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' ) + , (IoPin.SOUTH, None, 'p_pll_vco' , 'pll_vco' , 'pll_vco' ) , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms' , 'jtag_tms' ) , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo' , 'jtag_tdo' ) , (IoPin.EAST , None, 'ground_0' , 'vss' ) @@ -51,10 +52,13 @@ def scriptMain ( **kw ): , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck' , 'jtag_tck' ) , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi' , 'jtag_tdi' ) , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' ) + , (IoPin.EAST , None, 'p_b0' , 'b(0)' , 'b(0)' ) , (IoPin.NORTH, None, 'ioground_0' , 'iovss' ) , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' ) , (IoPin.NORTH, None, 'ground_1' , 'vss' ) - , (IoPin.NORTH, None, 'p_b0' , 'b(0)' , 'b(0)' ) + , (IoPin.NORTH, None, 'p_pll_test' , 'pll_test' , 'pll_test' ) + , (IoPin.NORTH, None, 'a0' , 'a0' , 'a0' ) + , (IoPin.NORTH, None, 'a1' , 'a1' , 'a1' ) , (IoPin.NORTH, None, 'p_sys_rst' , 'sys_rst' , 'sys_rst' ) , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' ) , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' ) @@ -73,7 +77,7 @@ def scriptMain ( **kw ): adderConf.editor = editor adderConf.useSpares = True adderConf.useClockTree = True - adderConf.useHFNS = True + #adderConf.useHFNS = True adderConf.cfg.katana.hTracksReservedMin = 9 adderConf.cfg.katana.vTracksReservedMin = 2 adderConf.bColumns = 2 -- 2.30.2