From a87dc8879f51197c87ad127dd1733e1e6eb649ee Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 9 May 2022 11:13:15 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index d2bfbb44a..700ac943c 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -4,6 +4,7 @@ * v0.00 05may2021 first created * v0.01 06may2021 initial first draft +* v0.02 08may2021 add scenarios / use-cased **Table of Contents** @@ -842,27 +843,23 @@ TLB entries to the PE in response. **Use-case: Matrix and Convolutions** +* **Horizontal-First**: (aka standard Cray Vectors) walk + through **elements** first before moving to next instruction +* **Vertical-First**: walk through **instructions** before + moving to next element. Currently managed by `svstep`, + ZOLC may be deployed to manage the stepping. + Imagine a large Matrix scenario, with several values close to zero that could be skipped: no need to include zero-multiplications, but a traditional CPU in no way can help: only by loading the data through the L1-L4 Cache and Virtual Memory Barriers is it possible to ascertain, retrospectively, that time and power had just been wasted. -SVP64 is able to do what is termed "Vertical-First" Vectorisation -*(walk first through a batch of instructions before explicitly -moving to the next element with `svstep`, and repeating the batch)*, +SVP64 is able to do what is termed "Vertical-First" Vectorisation, combined with SVREMAP Matrix Schedules. Imagine that SVREMAP has been extended, Snitch-style, to perform a deterministic memory-array walk of a large Matrix. -*
-* **Horizontal-First**: (aka standard Cray Vectors) walk through - **elements** first before moving to next instruction -* **Vertical-First**: walk through **instructions** before - moving to next element. Currently managed by `svstep`, - ZOLC may be deployed to manage the stepping. -
* - Let us also imagine that the Matrices are stored in Memory with PEs attached, and that the PEs are fully functioning Power ISA with Draft SVP64, but their Multiply capability is not as good as the main CPU. -- 2.30.2