From a880862628dd93f0adc2b0b2df2e2f1d2415b3a7 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 22 Sep 2013 13:28:12 +0200
Subject: [PATCH] mila: symplify usage

---
 examples/de0_nano/top.py | 16 +++++-----------
 miscope/mila.py          | 15 +++++++++++----
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index c75e4c77..67502829 100644
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -20,8 +20,7 @@ from migen.bank import csrgen
 
 from miscope.std.misc import *
 
-from miscope.trigger import Term, RangeDetector, EdgeDetector, Sum, Trigger
-from miscope.storage import Recorder
+from miscope.trigger import Term
 from miscope.miio import MiIo
 from miscope.mila import MiLa
 
@@ -37,9 +36,8 @@ from timings import *
 clk_freq	= 50*MHz
 
 # Mila Param
-trig_w		= 16
-dat_w		= 16
-rec_size	= 4096
+mila_width	= 16
+mila_depth  = 4096
 
 #==============================================================================
 #   M I S C O P E    E X A M P L E
@@ -51,17 +49,13 @@ class SoC(Module):
 		"mila":					2,
 	}
 
-
 	def __init__(self, platform):
 		# MiIo
 		self.submodules.miio = MiIo(8)
 
 		# MiLa
-		term = Term(trig_w)
-		trigger = Trigger(trig_w, [term])
-		recorder = Recorder(dat_w, rec_size)
-
-		self.submodules.mila = MiLa(trigger, recorder)
+		term = Term(mila_width)
+		self.submodules.mila = MiLa(mila_width, mila_depth, [term])
 	
 		# Uart2Csr
 		self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
diff --git a/miscope/mila.py b/miscope/mila.py
index 11197257..9d5ab7bb 100644
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -5,13 +5,20 @@ from migen.bus import csr
 from migen.bank import description, csrgen
 from migen.bank.description import *
 
+from miscope.trigger import Trigger
+from miscope.storage import Recorder
+
 class MiLa(Module, AutoCSR):
-	def __init__(self, trigger, recorder):
-		self.trigger = trigger
-		self.recorder = recorder
+	def __init__(self, width, depth, ports):
+		self.width = width
+
+		trigger = Trigger(width, ports)
+		recorder = Recorder(width, depth)
+
+		self.submodules.trigger = trigger
+		self.submodules.recorder = recorder
 
 		self.sink = trigger.sink
-		self.submodules += trigger, recorder
 
 		self.comb +=[
 			recorder.sink.stb.eq(trigger.source.stb),
-- 
2.30.2