From a8a619e1556e1e46e685bc707b807de7d86a0da8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Mar 2023 14:37:28 +0000 Subject: [PATCH] same reason for "`"s on pseudocode, Special Registers altered needs indentation --- openpower/sv/rfc/ls006.mdwn | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn index 3ac1e719d..5483eb404 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.mdwn @@ -154,7 +154,9 @@ operations. Special Registers altered: +``` CR0 (if Rc=1) +``` ---------- @@ -182,7 +184,9 @@ operations. Special Registers altered: +``` CR0 (if Rc=1) +``` ---------- @@ -212,7 +216,9 @@ operations. Special Registers altered: +``` CR1 (if Rc=1) +``` ---------- @@ -240,7 +246,9 @@ operations. Special Registers altered: +``` CR1 (if Rc=1) +``` ---------- @@ -305,8 +313,10 @@ operations. Special Registers altered: +``` CR1 (if Rc=1) FPCSR (TODO: which bits?) (if IT[0]=1) +``` ### Assembly Aliases @@ -368,8 +378,10 @@ operations. Special Registers altered: +``` CR1 (if Rc=1) FPCSR (TODO: which bits?) +``` ### Assembly Aliases @@ -654,9 +666,11 @@ that overflow. Special Registers altered: +``` CR0 (if Rc=1) XER SO, OV, OV32 (if OE=1) FPCSR (TODO: which bits?) +``` ### Assembly Aliases @@ -804,9 +818,11 @@ that overflow. Special Registers altered: +``` CR0 (if Rc=1) XER SO, OV, OV32 (if OE=1) FPCSR (TODO: which bits?) +``` ### Assembly Aliases -- 2.30.2