From a8a740f272a808a2694524b43fc33d2f0c0e3709 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 9 May 2018 15:06:13 -0700 Subject: [PATCH] i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL From the bspec docs for "Indirect State Pointers Disable": "At the completion of the post-sync operation associated with this pipe control packet, the indirect state pointers in the hardware are considered invalid" So the ISP disable is a post-sync type of operation which means that it should be combined with a CS stall. Without this, the simulator throws an error. Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable" Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable" Reviewed-by: Lionel Landwerlin --- src/intel/vulkan/genX_cmd_buffer.c | 1 + src/mesa/drivers/dri/i965/brw_pipe_control.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 526e18af108..afccad8ef80 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1434,6 +1434,7 @@ emit_isp_disable(struct anv_cmd_buffer *cmd_buffer) } anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { pc.IndirectStatePointersDisable = true; + pc.CommandStreamerStallEnable = true; } } diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 879bfb660ed..e31d625ddba 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -362,7 +362,8 @@ gen10_emit_isp_disable(struct brw_context *brw) PIPE_CONTROL_CS_STALL, NULL, 0, 0); brw_emit_pipe_control(brw, - PIPE_CONTROL_ISP_DIS, + PIPE_CONTROL_ISP_DIS | + PIPE_CONTROL_CS_STALL, NULL, 0, 0); brw->vs.base.push_constants_dirty = true; -- 2.30.2