From a8b45d7034eb482e217133180dff3e62bfb35150 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 3 Apr 2020 10:41:17 +0200 Subject: [PATCH] aco: implement 16-bit nir_op_frexp_sig/nir_op_frexp_exp MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Daniel Schürmann Part-of: --- .../compiler/aco_instruction_selection.cpp | 26 +++++++++++-------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index bd95d096bd2..1c601f161c1 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -1985,12 +1985,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) break; } case nir_op_frexp_sig: { - if (dst.size() == 1) { - bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst), - get_alu_src(ctx, instr->src[0])); - } else if (dst.size() == 2) { - bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst), - get_alu_src(ctx, instr->src[0])); + Temp src = get_alu_src(ctx, instr->src[0]); + if (dst.regClass() == v2b) { + Temp tmp = bld.vop1(aco_opcode::v_frexp_mant_f16, bld.def(v1), src); + bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp); + } else if (dst.regClass() == v1) { + bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst), src); + } else if (dst.regClass() == v2) { + bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst), src); } else { fprintf(stderr, "Unimplemented NIR instr bit size: "); nir_print_instr(&instr->instr, stderr); @@ -1999,12 +2001,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) break; } case nir_op_frexp_exp: { - if (instr->src[0].src.ssa->bit_size == 32) { - bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst), - get_alu_src(ctx, instr->src[0])); + Temp src = get_alu_src(ctx, instr->src[0]); + if (instr->src[0].src.ssa->bit_size == 16) { + Temp tmp = bld.vop1(aco_opcode::v_frexp_exp_i16_f16, bld.def(v1), src); + bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), tmp, Operand(0u)); + } else if (instr->src[0].src.ssa->bit_size == 32) { + bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst), src); } else if (instr->src[0].src.ssa->bit_size == 64) { - bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst), - get_alu_src(ctx, instr->src[0])); + bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst), src); } else { fprintf(stderr, "Unimplemented NIR instr bit size: "); nir_print_instr(&instr->instr, stderr); -- 2.30.2