From a8b4e6c45a352785320e573c2dc4afe6ce8e40b8 Mon Sep 17 00:00:00 2001 From: Steve Ellcey Date: Fri, 28 Sep 2018 14:44:15 +0000 Subject: [PATCH] re PR testsuite/87433 (gcc.dg/zero_bits_compound-1.c and gcc.target/aarch64/ashltidisi.c tests fail after combine two to two instruction patch on aarch64) 2018-09-28 Steve Ellcey PR testsuite/87433 * gcc.target/aarch64/ashltidisi.c: Expect 3 asr instructions instead of 4. From-SVN: r264692 --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/ashltidisi.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c62b37c67cc..fae9137ae81 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2018-09-26 Steve Ellcey + + PR testsuite/87433 + * gcc.target/aarch64/ashltidisi.c: Expect 3 asr instructions + instead of 4. + 2018-09-28 Steve Ellcey PR testsuite/87433 diff --git a/gcc/testsuite/gcc.target/aarch64/ashltidisi.c b/gcc/testsuite/gcc.target/aarch64/ashltidisi.c index 293a0f2563b..e2a09975801 100644 --- a/gcc/testsuite/gcc.target/aarch64/ashltidisi.c +++ b/gcc/testsuite/gcc.target/aarch64/ashltidisi.c @@ -45,5 +45,5 @@ main (int argc, char **argv) return 0; } -/* { dg-final { scan-assembler-times "asr" 4 } } */ +/* { dg-final { scan-assembler-times "asr" 3 } } */ /* { dg-final { scan-assembler-not "extr\t" } } */ -- 2.30.2