From a8ba697c1ec3e07e331cba85e67bf5c2b8d41e57 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Wed, 23 May 2012 15:37:11 -0400
Subject: [PATCH] radeon/llvm: Remove AMDIL EXP* instructions

---
 src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl | 11 ++---------
 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp |  3 +++
 src/gallium/drivers/radeon/AMDGPUUtil.cpp         |  1 -
 src/gallium/drivers/radeon/AMDILInstructions.td   |  2 --
 src/gallium/drivers/radeon/R600Instructions.td    |  5 ++---
 5 files changed, 7 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index 64a29285782..f0cb9ae0bfc 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -31,10 +31,6 @@
 use warnings;
 use strict;
 
-my @F32_MULTICLASSES = qw {
-  UnaryIntrinsicFloatScalar
-};
-
 my @I32_MULTICLASSES = qw {
   BinaryOpMCi32Const
 };
@@ -52,14 +48,11 @@ my $FILE_TYPE = $ARGV[0];
 
 open AMDIL, '<', 'AMDILInstructions.td';
 
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'SMULHI_i32', 'SMUL_i32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'SMULHI_i32', 'SMUL_i32', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
 
 while (<AMDIL>) {
   if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
-    if (grep {$_ eq $2} @F32_MULTICLASSES) {
-      push @INST_ENUMS, "$1\_f32";
-
-    } elsif (grep {$_ eq $2} @I32_MULTICLASSES) {
+    if (grep {$_ eq $2} @I32_MULTICLASSES) {
       push @INST_ENUMS, "$1\_i32";
     }
   } elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 3ce446f6744..ea7046102e8 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -30,6 +30,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
   // Library functions.  These default to Expand, but we have instructions
   // for them.
   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
+  setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
 }
@@ -55,6 +56,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     default: return Op;
     case AMDGPUIntrinsic::AMDIL_abs:
       return LowerIntrinsicIABS(Op, DAG);
+    case AMDGPUIntrinsic::AMDIL_exp:
+      return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
     case AMDGPUIntrinsic::AMDGPU_lrp:
       return LowerIntrinsicLRP(Op, DAG);
     case AMDGPUIntrinsic::AMDIL_fraction:
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index 20831a613b7..86c01007330 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -55,7 +55,6 @@ bool AMDGPU::isTransOp(unsigned opcode)
     case AMDIL::MUL_LIT_eg:
     case AMDIL::SHR_i32:
     case AMDIL::SIN_f32:
-    case AMDIL::EXP_f32:
     case AMDIL::EXP_IEEE_r600:
     case AMDIL::EXP_IEEE_eg:
     case AMDIL::LOG_CLAMPED_r600:
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 85ece1e2f51..304d91e4da3 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -218,8 +218,6 @@ defm TAN : UnaryIntrinsicFloatScalar<IL_OP_TAN, int_AMDIL_tan>;
 defm SIN : UnaryIntrinsicFloatScalar<IL_OP_SIN, int_AMDIL_sin>;
 defm COS : UnaryIntrinsicFloatScalar<IL_OP_COS, int_AMDIL_cos>;
 defm SQRT : UnaryIntrinsicFloatScalar<IL_OP_SQRT, int_AMDIL_sqrt>;
-defm EXP : UnaryIntrinsicFloatScalar<IL_OP_EXP, int_AMDIL_exp>;
-defm EXPVEC : UnaryIntrinsicFloat<IL_OP_EXP_VEC, int_AMDIL_exp_vec>;
 defm SQRTVEC : UnaryIntrinsicFloat<IL_OP_SQRT_VEC, int_AMDIL_sqrt_vec>;
 defm COSVEC : UnaryIntrinsicFloat<IL_OP_COS_VEC, int_AMDIL_cos_vec>;
 defm SINVEC : UnaryIntrinsicFloat<IL_OP_SIN_VEC, int_AMDIL_sin_vec>;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 4737f1ca9f4..c1458fba482 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -622,9 +622,8 @@ class CUBE_Common <bits<32> inst> : InstR600 <
 
 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
   inst, "EXP_IEEE",
-  []> {
-  let AMDILOp = AMDILInst.EXP_f32;
-}
+  [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
+>;
 
 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
   inst, "FLT_TO_INT", []> {
-- 
2.30.2