From a8e20f447c64d485901b62b4dc48d4761fc9f09a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 17:46:45 -0700 Subject: [PATCH] spi: include mem region (#23) --- src/main/scala/devices/spi/TLSPI.scala | 10 +--------- src/main/scala/devices/spi/TLSPIFlash.scala | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala index 5833fad..5c5b9bf 100644 --- a/src/main/scala/devices/spi/TLSPI.scala +++ b/src/main/scala/devices/spi/TLSPI.scala @@ -109,15 +109,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule { require(isPow2(c.rSize)) - val device = new SimpleDevice("spi", Seq("sifive,spi0")) { - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - val rangesSeq = resources("ranges").map(_.value) - val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq) - Description(name, mapping ++ ranges) - } - } - + val device = new SimpleDevice("spi", Seq("sifive,spi0")) val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w) val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) } diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala index fc786f5..8968c69 100644 --- a/src/main/scala/devices/spi/TLSPIFlash.scala +++ b/src/main/scala/devices/spi/TLSPIFlash.scala @@ -95,7 +95,7 @@ abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Paramet require(isPow2(c.fSize)) val fnode = TLManagerNode(1, TLManagerParameters( address = Seq(AddressSet(c.fAddress, c.fSize-1)), - resources = Seq(Resource(device, "ranges")), + resources = device.reg("mem"), regionType = RegionType.UNCACHED, executable = true, supportsGet = TransferSizes(1, 1), -- 2.30.2