From a8fbc4ec76169a6d735817df2aa8bc2085df5ac8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 30 Apr 2006 01:46:00 -0400 Subject: [PATCH] Got hello world to work! arch/sparc/isa/decoder.isa: Made sure if a register was assigned to along some control path, then all paths on which no exception would block commit set a value as well. Also, Rs1 is treated as signed for bpr instructions. arch/sparc/isa/formats/integerop.isa: Added an IntOpImm11 class which sign extends the SIMM11 immediate field. arch/sparc/isa/formats/mem.isa: Fixed how offsets are used, and how disassembly is generated. arch/sparc/linux/process.cc: Added fstat and exit_group syscalls. --HG-- extra : convert_revision : 3b4427d239d254a92179a4137441125b8a364264 --- arch/sparc/isa/decoder.isa | 33 ++++++++++++++++------------ arch/sparc/isa/formats/integerop.isa | 15 +++++++++++++ arch/sparc/isa/formats/mem.isa | 10 ++++++--- arch/sparc/linux/process.cc | 4 ++-- 4 files changed, 43 insertions(+), 19 deletions(-) diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa index ca409fa66..b9e83afd6 100644 --- a/arch/sparc/isa/decoder.isa +++ b/arch/sparc/isa/decoder.isa @@ -38,37 +38,37 @@ decode OP default Unknown::unknown() format BranchSplit { 0x1: bpreq({{ - if(Rs1 == 0) + if(Rs1.sdw == 0) NNPC = xc->readPC() + disp; else handle_annul }}); 0x2: bprle({{ - if(Rs1 <= 0) + if(Rs1.sdw <= 0) NNPC = xc->readPC() + disp; else handle_annul }}); 0x3: bprl({{ - if(Rs1 < 0) + if(Rs1.sdw < 0) NNPC = xc->readPC() + disp; else handle_annul }}); 0x5: bprne({{ - if(Rs1 != 0) + if(Rs1.sdw != 0) NNPC = xc->readPC() + disp; else handle_annul }}); 0x6: bprg({{ - if(Rs1 > 0) + if(Rs1.sdw > 0) NNPC = xc->readPC() + disp; else handle_annul }}); 0x7: bprge({{ - if(Rs1 >= 0) + if(Rs1.sdw >= 0) NNPC = xc->readPC() + disp; else handle_annul @@ -350,11 +350,15 @@ decode OP default Unknown::unknown() { 0x0: movcci({{ if(passesCondition(CcrIcc, COND4)) - Rd = (I ? SIMM11 : RS2); + Rd = Rs2_or_imm11; + else + Rd = Rd; }}); 0x2: movccx({{ if(passesCondition(CcrXcc, COND4)) - Rd = (I ? SIMM11 : RS2); + Rd = Rs2_or_imm11; + else + Rd = Rd; }}); } } @@ -373,16 +377,17 @@ decode OP default Unknown::unknown() count += oneBits[temp & 0xF]; temp = temp >> 4; } + Rd = count; }}); } 0x2F: decode RCOND3 { - 0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}}); - 0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}}); - 0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}}); - 0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}}); - 0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}}); - 0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}}); + 0x1: movreq({{Rd = (Rs1 == 0) ? Rs2_or_imm10 : Rd;}}); + 0x2: movrle({{Rd = (Rs1 <= 0) ? Rs2_or_imm10 : Rd;}}); + 0x3: movrl({{Rd = (Rs1 < 0) ? Rs2_or_imm10 : Rd;}}); + 0x5: movrne({{Rd = (Rs1 != 0) ? Rs2_or_imm10 : Rd;}}); + 0x6: movrg({{Rd = (Rs1 > 0) ? Rs2_or_imm10 : Rd;}}); + 0x7: movrge({{Rd = (Rs1 >= 0) ? Rs2_or_imm10 : Rd;}}); } 0x30: decode RD { 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa index 407a3e3cd..881154b67 100644 --- a/arch/sparc/isa/formats/integerop.isa +++ b/arch/sparc/isa/formats/integerop.isa @@ -61,6 +61,21 @@ output header {{ } }; + /** + * Base class for 11 bit immediate integer operations. + */ + class IntOpImm11 : public IntOpImm + { + protected: + // Constructor + IntOpImm11(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + IntOpImm(mnem, _machInst, __opClass) + { + imm = sign_ext(SIMM11, 11); + } + }; + /** * Base class for 13 bit immediate integer operations. */ diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa index ab8b85a94..12dae57e5 100644 --- a/arch/sparc/isa/formats/mem.isa +++ b/arch/sparc/isa/formats/mem.isa @@ -30,8 +30,9 @@ output header {{ // Constructor MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - Mem(mnem, _machInst, __opClass), imm(SIMM13) + Mem(mnem, _machInst, __opClass) { + imm = sign_ext(SIMM13, 13); } std::string generateDisassembly(Addr pc, @@ -84,7 +85,10 @@ output decoder {{ } ccprintf(response, "[ "); printReg(response, _srcRegIdx[!save ? 0 : 1]); - ccprintf(response, " + 0x%x ]", imm); + if(imm >= 0) + ccprintf(response, " + 0x%x ]", imm); + else + ccprintf(response, " + -0x%x ]", -imm); if(load) { ccprintf(response, ", "); @@ -127,7 +131,7 @@ let {{ def doMemFormat(code, load, store, name, Name, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2;' - addrCalcImm = 'EA = Rs1 + SIMM13;' + addrCalcImm = 'EA = Rs1 + imm;' iop = InstObjParams(name, Name, 'Mem', code, opt_flags, ("ea_code", addrCalcReg), ("load", load), ("store", store)) diff --git a/arch/sparc/linux/process.cc b/arch/sparc/linux/process.cc index 4818f1fcc..71be6a83a 100644 --- a/arch/sparc/linux/process.cc +++ b/arch/sparc/linux/process.cc @@ -155,7 +155,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 59 */ SyscallDesc("execve", unimplementedFunc), /* 60 */ SyscallDesc("umask", unimplementedFunc), /* 61 */ SyscallDesc("chroot", unimplementedFunc), - /* 62 */ SyscallDesc("fstat", unimplementedFunc), + /* 62 */ SyscallDesc("fstat", fstatFunc), /* 63 */ SyscallDesc("fstat64", unimplementedFunc), /* 64 */ SyscallDesc("getpagesize", unimplementedFunc), /* 65 */ SyscallDesc("msync", unimplementedFunc), @@ -281,7 +281,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 185 */ SyscallDesc("setpgid", unimplementedFunc), /* 186 */ SyscallDesc("fremovexattr", unimplementedFunc), /* 187 */ SyscallDesc("tkill", unimplementedFunc), - /* 188 */ SyscallDesc("exit_group", unimplementedFunc), + /* 188 */ SyscallDesc("exit_group", exitFunc), /* 189 */ SyscallDesc("uname", unameFunc), /* 190 */ SyscallDesc("init_module", unimplementedFunc), /* 191 */ SyscallDesc("personality", unimplementedFunc), -- 2.30.2