From a9083bdb71117a84a81909a201657b192c37a027 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 18 Jul 2018 09:02:35 -0700 Subject: [PATCH] iris: don't emit SO_BUFFERS and SO_DECL_LIST unless streamout is enabled Otherwise on the first draw, if XFB isn't enabled, we get a pile of MI_NOOPS where SO_BUFFERS should be --- src/gallium/drivers/iris/iris_state.c | 45 ++++++++++++++------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 6efc99b66cd..0cecb307a88 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -2940,32 +2940,31 @@ iris_upload_render_state(struct iris_context *ice, } } - if (dirty & IRIS_DIRTY_SO_BUFFERS) { - iris_batch_emit(batch, genx->so_buffers, - 4 * 4 * GENX(3DSTATE_SO_BUFFER_length)); - for (int i = 0; i < 4; i++) { - struct iris_stream_output_target *tgt = - (void *) ice->state.so_target[i]; - if (tgt) { - iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer), - true); - iris_use_pinned_bo(batch, iris_resource_bo(tgt->offset.res), true); + if (ice->state.streamout_active) { + if (dirty & IRIS_DIRTY_SO_BUFFERS) { + iris_batch_emit(batch, genx->so_buffers, + 4 * 4 * GENX(3DSTATE_SO_BUFFER_length)); + for (int i = 0; i < 4; i++) { + struct iris_stream_output_target *tgt = + (void *) ice->state.so_target[i]; + if (tgt) { + iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer), + true); + iris_use_pinned_bo(batch, iris_resource_bo(tgt->offset.res), + true); + } } } - } - if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) { - uint32_t *decl_list = - ice->state.streamout + GENX(3DSTATE_STREAMOUT_length); - iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2)); - } + if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) { + uint32_t *decl_list = + ice->state.streamout + GENX(3DSTATE_STREAMOUT_length); + iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2)); + } - if (dirty & IRIS_DIRTY_STREAMOUT) { - const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast; + if (dirty & IRIS_DIRTY_STREAMOUT) { + const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast; - if (!ice->state.streamout_active) { - iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol); - } else { uint32_t dynamic_sol[GENX(3DSTATE_STREAMOUT_length)]; iris_pack_command(GENX(3DSTATE_STREAMOUT), dynamic_sol, sol) { sol.SOFunctionEnable = true; @@ -2981,6 +2980,10 @@ iris_upload_render_state(struct iris_context *ice, iris_emit_merge(batch, ice->state.streamout, dynamic_sol, GENX(3DSTATE_STREAMOUT_length)); } + } else { + if (dirty & IRIS_DIRTY_STREAMOUT) { + iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol); + } } if (dirty & IRIS_DIRTY_CLIP) { -- 2.30.2