From a916d4ae6850cbfc3fda72147fdbbafe1e1b8040 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 16 Jun 2020 16:21:47 +0200 Subject: [PATCH] Fix CSR attribute error --- gram/phy/ecp5ddrphy.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index fc6c27f..ad4b7c9 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -251,18 +251,18 @@ class ECP5DDRPHY(Peripheral, Elaboratable): wrpntr = Signal(3) rdly = Signal(7) with m.If(self._dly_sel.w_data[i]): - with m.If(self._rdly_dq_rst.re): + with m.If(self._rdly_dq_rst.w_stb): m.d.sync += rdly.eq(0) - with m.Elif(self._rdly_dq_inc.re): + with m.Elif(self._rdly_dq_inc.w_stb): m.d.sync += rdly.eq(rdly + 1) datavalid = Signal() burstdet = Signal() dqs_read = Signal() dqs_bitslip = Signal(2) with m.If(self._dly_sel.w_data[i]): - with m.If(self._rdly_dq_bitslip_rst.re): + with m.If(self._rdly_dq_bitslip_rst.w_stb): m.d.sync += dqs_bitslip.eq(0) - with m.Elif(self._rdly_dq_bitslip.re): + with m.Elif(self._rdly_dq_bitslip.w_stb): m.d.sync += dqs_bitslip.eq(dqs_bitslip + 1) dqs_cases = {} for j, b in enumerate(range(-2, 2)): @@ -313,7 +313,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): ) burstdet_d = Signal() m.d.sync += burstdet_d.eq(burstdet) - with m.If(self._burstdet_clr.re): + with m.If(self._burstdet_clr.w_stb): m.d.sync += self._burstdet_seen.status[i].eq(0) with m.If(burstdet & ~burstdet_d): m.d.sync += self._burstdet_seen.status[i].eq(1) -- 2.30.2