From a9221d820a24b7e00d2be4e16f2a77cfc7438aae Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 21 May 2018 15:58:32 +0000 Subject: [PATCH] [AArch64][committed] Fix gcc.target/aarch64/vec_init_1.c for tiny and large mcmodels This recently-committed test fails the INS scan for tiny and large memory models. That is because instead of the: make_vector: adrp x1, a adrp x0, b movi v0.4s, 0 ldr s2, [x1, #:lo12:a] ldr s1, [x0, #:lo12:b] ins v0.s[2], v2.s[0] ins v0.s[3], v1.s[0] ret That we generate for the default small model, we end up with a simple register addressing mode with no addend/offset for the lane load: make_vector: movi v0.4s, 0 adr x1, a adr x0, b ld1 {v0.s}[2], [x1] ld1 {v0.s}[3], [x0] ret and make_vector: movi v0.4s, 0 adrp x0, .LC0 ldr x1, [x0, #:lo12:.LC0] adrp x0, .LC1 ldr x0, [x0, #:lo12:.LC1] ld1 {v0.s}[2], [x1] ld1 {v0.s}[3], [x0] ret So we end up merging the load and the lane insert. This patch adjusts the testcase to scan for the right thing accordingly. Checked that the testcase passes with -mcmodel=tiny, -mcmodel=small, -mcmodel=large. * gcc.target/aarch64/vec_init_1.c: Scan for LD1 instead of INS for tiny and large memory models. From-SVN: r260474 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/vec_init_1.c | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d028fcd5c51..781ae5d4eb0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-05-21 Kyrylo Tkachov + + * gcc.target/aarch64/vec_init_1.c: Scan for LD1 instead of INS for + tiny and large memory models. + 2018-04-04 Ed Schonberg * gnat.dg/suppress_initialization.adb, diff --git a/gcc/testsuite/gcc.target/aarch64/vec_init_1.c b/gcc/testsuite/gcc.target/aarch64/vec_init_1.c index e245dc18b63..c8b48dac452 100644 --- a/gcc/testsuite/gcc.target/aarch64/vec_init_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vec_init_1.c @@ -25,7 +25,11 @@ main (int argc, char **argv) return 0; } -/* { dg-final { scan-assembler-times "ins\\t" 2 } } */ +/* For memory models that don't have an addend on the lane value + load we can merge the load and lane insert into an LD1. + For others we expect LDR + INS sequences. */ +/* { dg-final { scan-assembler-times "ld1\\t" 2 { target { aarch64_tiny || aarch64_large } } } } */ +/* { dg-final { scan-assembler-times "ins\\t" 2 { target aarch64_small } } } */ /* What we want to check, is that make_vector does not stp the whole vector to the stack. Unfortunately here we scan the body of main() too, which may be a bit fragile - the test is currently passing only because of the option -- 2.30.2