From a92632fbb1b13d0b632126e0845ba5f6cb4e3c7c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 May 2018 18:04:39 +0100
Subject: [PATCH] more slides

---
 simple_v_extension/simple_v_chennai_2018.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 817e317af..56e99d013 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -92,7 +92,7 @@ function op_add(rd, rs1, rs2, predr) # add not VADD!
   for (i=0; i < MIN(VL, vectorlen[rd]); i++)
     if (ireg[predr] & 1<<i) # predication uses intregs
        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-    if (reg_is_vectorised[rd]) \{ id += 1; \}
+    if (reg_is_vectorised[rd]) \{ id += 1; \}
     if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
     if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
 \end{semiverbatim}
-- 
2.30.2