From a933047a8e43c788e13d7e1e85c0144961ae0974 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 18:45:31 +0100 Subject: [PATCH] initialise XER from simulation --- src/soc/regfile/regfiles.py | 2 +- src/soc/simple/test/test_core.py | 23 +++++++++++++++++++++-- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 5ba3b917..ba732bed 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -102,7 +102,7 @@ class XERRegs(VirtualRegPort): CA=1 # CA and CA32 OV=2 # OV and OV32 def __init__(self): - super().__init__(6, 2) + super().__init__(6, 3) self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines) self.write_port("dest1"), self.write_port("dest2"), diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 1e95f433..68357ac2 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -1,12 +1,13 @@ -from nmigen import Module, Signal +from nmigen import Module, Signal, Cat from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest +from soc.decoder.isa.caller import special_sprs from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_decoder2 import PowerDecode2 from soc.decoder.isa.all import ISA -from soc.decoder.power_enums import Function +from soc.decoder.power_enums import Function, XER_bits from soc.simple.core import NonProductionCore @@ -149,6 +150,24 @@ class TestRunner(FHDLTestCase): for i in range(32): yield core.regs.int.regs[i].reg.eq(test.regs[i]) + # set up XER + xregs = core.regs.xer + print ("sprs", test.sprs) + if special_sprs['XER'] in test.sprs: + xer = test.sprs[special_sprs['XER']] + sobit = xer[XER_bits['SO']].asint() + yield xregs.regs[xregs.SO].reg.eq(sobit) + cabit = xer[XER_bits['CA']].asint() + ca32bit = xer[XER_bits['CA32']].asint() + yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit)) + ovbit = xer[XER_bits['OV']].asint() + ov32bit = xer[XER_bits['OV32']].asint() + yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit)) + else: + yield xregs.regs[xregs.SO].reg.eq(0) + yield xregs.regs[xregs.OV].reg.eq(0) + yield xregs.regs[xregs.CA].reg.eq(0) + index = sim.pc.CIA.value//4 while index < len(instructions): ins, code = instructions[index] -- 2.30.2