From a9372607438287c72012a4a487eb1ad58389621a Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Oct 2018 07:50:08 +0100
Subject: [PATCH] add sv_float32_t override, use explicit float32_t typecast
 for now

---
 riscv/decode.h            |  2 +-
 riscv/insns/fmax_s.h      |  6 +++---
 riscv/insns/fmin_s.h      |  6 +++---
 riscv/insns/fmsub_s.h     |  2 +-
 riscv/insns/fnmadd_s.h    |  2 +-
 riscv/insns/fnmsub_s.h    |  2 +-
 riscv/sv_insn_redirect.cc |  3 ++-
 riscv/sv_insn_redirect.h  |  2 +-
 riscv/sv_reg.h            | 16 ++++++++++++++++
 9 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index 2257327..53e8378 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -250,7 +250,7 @@ inline freg_t freg(float128_t f) { return f; }
 #define F32_SIGN ((uint32_t)1 << 31)
 #define F64_SIGN ((uint64_t)1 << 63)
 #define fsgnj32(a, b, n, x) \
-  f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
+  f32((((float32_t)f32(a)).v & ~F32_SIGN) | ((((x) ? ((float32_t)f32(a)).v : (n) ? F32_SIGN : 0) ^ ((float32_t)f32(b)).v) & F32_SIGN))
 #define fsgnj64(a, b, n, x) \
   f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
 
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 41d8f92..2d1f7cc 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,9 +1,9 @@
 require_extension('F');
 require_fp;
 bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) ||
-               (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
+               (f32_eq(f32(FRS2), f32(FRS1)) && (((float32_t)f32(FRS2)).v & F32_SIGN));
+if (isNaNF32UI(((float32_t)f32(FRS1)).v) && isNaNF32UI(((float32_t)f32(FRS2)).v))
   WRITE_FRD(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD(greater || isNaNF32UI(((float32_t)f32(FRS2)).v) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 19e1193..4bc595b 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,9 +1,9 @@
 require_extension('F');
 require_fp;
 bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
-            (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
+            (f32_eq(f32(FRS1), f32(FRS2)) && (((float32_t)f32(FRS1)).v & F32_SIGN));
+if (isNaNF32UI(((float32_t)f32(FRS1)).v) && isNaNF32UI(((float32_t)f32(FRS2)).v))
   WRITE_FRD(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD(less || isNaNF32UI(((float32_t)f32(FRS2)).v) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index d46c887..f48d974 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(((float32_t)f32(FRS3)).v ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 1c2996e..476c9a4 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD(f32_mulAdd(f32(((float32_t)f32(FRS1)).v ^ F32_SIGN), f32(FRS2), f32(((float32_t)f32(FRS3)).v ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 4c61fc7..132d970 100644
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
+WRITE_FRD(f32_mulAdd(f32(((float32_t)f32(FRS1)).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
 set_fp_exceptions;
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index e93ace4..d94671e 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -5,7 +5,8 @@
 
 void (sv_proc_t::WRITE_FRD)(sv_float32_t value)
 {
-    fprintf(stderr, "WRITE_FRD sv_float32_t %f\n", (float)value.v);
+    fprintf(stderr, "WRITE_FRD sv_float32_t %f\n",
+            (float)((float32_t)value).v);
     DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 56cf9a8..bbf62f3 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -56,7 +56,7 @@ class insn_t;
 
 //typedef reg_t sv_reg_t;
 //typedef sreg_t sv_sreg_t;
-typedef float32_t sv_float32_t;
+//typedef float32_t sv_float32_t;
 typedef float64_t sv_float64_t;
 typedef float128_t sv_float128_t;
 //typedef freg_t sv_freg_t;
diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index b6f003e..70e1533 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -91,4 +91,20 @@ public:
   operator freg_t() const& { return reg; }
 };
 
+class sv_float32_t : public sv_regbase_t {
+public:
+    sv_float32_t(float32_t _reg) : sv_regbase_t(), reg(_reg) { } // default elwidth
+    sv_float32_t(float32_t _reg, uint8_t _elwidth) :
+                sv_regbase_t(_elwidth), reg(_reg)
+                                                {}
+    sv_float32_t(float32_t _reg, int xlen, uint8_t _elwidth) :
+                sv_regbase_t(xlen, _elwidth), reg(_reg)
+                                                {}
+
+    float32_t reg;
+public:
+
+  operator float32_t() const& { return reg; }
+};
+
 #endif
-- 
2.30.2