From a952f9655ead10b3a80019276733913eb58d3059 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Apr 2020 17:36:26 +0100 Subject: [PATCH] test fixedload --- libreriscv | 2 +- src/soc/decoder/power_pseudo.py | 14 +++++++++++++- src/soc/decoder/pseudo/parser.py | 11 ++++++++++- src/soc/decoder/pseudo/pywriter.py | 2 ++ 4 files changed, 26 insertions(+), 3 deletions(-) diff --git a/libreriscv b/libreriscv index 36ca9489..6ad52e42 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 36ca948926f4c13b6e121948606a4d1aed8394f6 +Subproject commit 6ad52e429bfcc8f815de14109833eb9288bc9c86 diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py index c837ce86..9ed82951 100644 --- a/src/soc/decoder/power_pseudo.py +++ b/src/soc/decoder/power_pseudo.py @@ -107,8 +107,20 @@ RS <- RS + 1 print(RS) """ +testcat = """ +RT <- (load_data[56:63] || load_data[48:55] + || load_data[40:47] || load_data[32:39] + || load_data[24:31] || load_data[16:23] + || load_data[8:15] || load_data[0:7]) +""" + +testgpr = """ +GPR(5) <- x +""" #code = testmul -code = testgetzero +#code = testgetzero +#code = testcat +code = testgpr #code = testreg #code = cnttzd #code = cmpi diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py index 9cd669a0..437310ef 100644 --- a/src/soc/decoder/pseudo/parser.py +++ b/src/soc/decoder/pseudo/parser.py @@ -305,6 +305,7 @@ class PowerParser: #p[0] = ast.Discard(p[1]) p[0] = p[1] else: + name = None if isinstance(p[1], ast.Name): name = p[1].id elif isinstance(p[1], ast.Subscript): @@ -312,8 +313,16 @@ class PowerParser: if name in self.gprs: # add to list of uninitialised self.uninit_regs.add(name) + elif isinstance(p[1], ast.Call) and p[1].func.id == 'GPR': + print(astor.dump_tree(p[1])) + # replace GPR(x) with GPR[x] + idx = p[1].args[0] + p[1] = ast.Subscript(p[1].func, idx) + else: + print ("help, help") + print(astor.dump_tree(p[1])) print("expr assign", name, p[1]) - if name in self.gprs: + if name and name in self.gprs: self.write_regs.add(name) # add to list of regs to write p[0] = Assign(p[1], p[3]) diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py index ddc4dc59..2bc9dc5e 100644 --- a/src/soc/decoder/pseudo/pywriter.py +++ b/src/soc/decoder/pseudo/pywriter.py @@ -79,5 +79,7 @@ class PyISAWriter(ISA): if __name__ == '__main__': isa = PyISAWriter() + isa.write_pysource('fixedload') + exit(0) isa.write_pysource('comparefixed') isa.write_pysource('fixedarith') -- 2.30.2