From a98694517a54edf47be4d29a55a51ea26f8f51e8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Mar 2021 00:28:49 +0000 Subject: [PATCH] add SPBlock_512W64B8W.v blackbox file --- src/soc/litex/florent/Makefile | 1 + src/soc/litex/florent/SPBlock_512W64B8W.v | 7 +++++++ 2 files changed, 8 insertions(+) create mode 100644 src/soc/litex/florent/SPBlock_512W64B8W.v diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile index ab73b7bf..434bcda3 100644 --- a/src/soc/litex/florent/Makefile +++ b/src/soc/litex/florent/Makefile @@ -10,6 +10,7 @@ ls180: yosys -p 'read_verilog libresoc.v' \ -p 'write_ilang libresoc_cvt.il' yosys -p 'read_verilog ls180.v' \ + -p 'read_verilog SPBlock_512W64B8W.v' \ -p 'write_ilang ls180_cvt.il' yosys -p 'read_ilang ls180_cvt.il' \ -p 'read_ilang libresoc_cvt.il' \ diff --git a/src/soc/litex/florent/SPBlock_512W64B8W.v b/src/soc/litex/florent/SPBlock_512W64B8W.v new file mode 100644 index 00000000..ddab9684 --- /dev/null +++ b/src/soc/litex/florent/SPBlock_512W64B8W.v @@ -0,0 +1,7 @@ +(* blackbox = 1 *) +module SPBlock_512W64B8W(input [8:0] a, + input [63:0] d, + output [63:0] q, + input [7:0] we, + input clk); +endmodule // SPBlock_512W64B8W -- 2.30.2