From a99aa9c7fd56e97ebb316ac9b83440f522a622ad Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 9 May 2015 16:24:28 +0200 Subject: [PATCH] uart: rename wishbone to bridge --- misoclib/com/liteeth/example_designs/targets/base.py | 2 +- misoclib/com/litepcie/example_designs/targets/dma.py | 2 +- misoclib/com/uart/{wishbone.py => bridge.py} | 0 misoclib/mem/litesata/example_designs/targets/bist.py | 2 +- misoclib/tools/litescope/example_designs/targets/simple.py | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename misoclib/com/uart/{wishbone.py => bridge.py} (100%) diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 99b117c8..14c9cbfa 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.uart.wishbone import UARTWishboneBridge +from misoclib.com.uart.bridge import UARTWishboneBridge from misoclib.com.liteeth.common import * from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py index c4c9e550..90f3ec88 100644 --- a/misoclib/com/litepcie/example_designs/targets/dma.py +++ b/misoclib/com/litepcie/example_designs/targets/dma.py @@ -7,7 +7,7 @@ from migen.genlib.misc import timeline from misoclib.soc import SoC from misoclib.tools.litescope.common import * -from misoclib.com.uart.wishbone import UARTWishboneBridge +from misoclib.com.uart.bridge import UARTWishboneBridge from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY from misoclib.com.litepcie.core import Endpoint diff --git a/misoclib/com/uart/wishbone.py b/misoclib/com/uart/bridge.py similarity index 100% rename from misoclib/com/uart/wishbone.py rename to misoclib/com/uart/bridge.py diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py index ce7d53a1..60f7fcd9 100644 --- a/misoclib/mem/litesata/example_designs/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import * from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm -from misoclib.com.uart.wishbone import UARTWishboneBridge +from misoclib.com.uart.bridge import UARTWishboneBridge from misoclib.mem.litesata.common import * from misoclib.mem.litesata.phy import LiteSATAPHY diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py index 26853f7e..f9246053 100644 --- a/misoclib/tools/litescope/example_designs/targets/simple.py +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.tools.litescope.frontend.io import LiteScopeIO from misoclib.tools.litescope.frontend.la import LiteScopeLA -from misoclib.com.uart.wishbone import UARTWishboneBridge +from misoclib.com.uart.bridge import UARTWishboneBridge class LiteScopeSoC(SoC, AutoCSR): csr_map = { -- 2.30.2