From a9b1022cede509b07e94b7d1f6fdcf8bc657d60f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 May 2023 16:37:26 +0100 Subject: [PATCH] ld/st mismatch in power_insn.py and sv_analysis.py some EXTRA slots run empty now due to source/dest being the same register (s:RA;d:RA) --- openpower/isatables/LDSTRM-2P-2S1D.csv | 12 ++++++------ src/openpower/decoder/power_insn.py | 18 ++++++++++-------- src/openpower/sv/sv_analysis.py | 12 ++++-------- 3 files changed, 20 insertions(+), 22 deletions(-) diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv index d850f492..3494baca 100644 --- a/openpower/isatables/LDSTRM-2P-2S1D.csv +++ b/openpower/isatables/LDSTRM-2P-2S1D.csv @@ -34,9 +34,9 @@ lwaux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lhaux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA lfsux,LDST_IDX,,2P,EXTRA2,EN,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA lfdux,LDST_IDX,,2P,EXTRA2,EN,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,RA -stdux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stwux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stbux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -sthux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA -stfsux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:FRS;s:RA,s:RB,0,RA,RB,FRS,0,0,0,RA -stfdux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:FRS;s:RA,s:RB,0,RA,RB,FRS,0,0,0,RA +stdux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stwux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stbux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA +sthux,LDST_IDX,,2P,EXTRA3,EN,s:RS;s:RA;d:RA,s:RB,0,0,RA_OR_ZERO,RB,RS,0,0,0,RA +stfsux,LDST_IDX,,2P,EXTRA3,EN,s:FRS;s:RA;d:RA,s:RB,0,0,RA,RB,FRS,0,0,0,RA +stfdux,LDST_IDX,,2P,EXTRA3,EN,s:FRS;s:RA;d:RA,s:RB,0,0,RA,RB,FRS,0,0,0,RA diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index c1b66de3..44888ea2 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1262,6 +1262,8 @@ class ExtendableOperand(DynamicOperand): that_extra_reg = pairs.get(extra_reg, extra_reg) if this_extra_reg is that_extra_reg: bits = tuple(self.record.extra_idx(key=key, regtype=rtype)) + if len(bits) == 0: # empty slot, do not attempt to use it! + continue if this_extra_reg in found: assert found[this_extra_reg] == bits # check identical bits continue # skip - already found @@ -2164,8 +2166,9 @@ class NormalMRRM(MRBaseRM, NormalBaseRM): RG: BaseRM.mode[4] -class NormalFFRc1RM(FFRc1BaseRM, NormalBaseRM): +class NormalFFRc1RM(FFRc1BaseRM, VLiBaseRM, NormalBaseRM): """normal: Rc=1: ffirst CR sel""" + VLi: BaseRM.mode[0] inv: BaseRM.mode[2] CR: BaseRM.mode[3, 4] @@ -2175,8 +2178,8 @@ class NormalFFRc1RM(FFRc1BaseRM, NormalBaseRM): class NormalFFRc0RM(FFRc0BaseRM, VLiBaseRM, NormalBaseRM): """normal: Rc=0: ffirst z/nonz""" + VLi: BaseRM.mode[0] inv: BaseRM.mode[2] - VLi: BaseRM.mode[3] RC1: BaseRM.mode[4] def specifiers(self, record): @@ -2226,7 +2229,7 @@ class LDSTImmPostRM(LDSTImmBaseRM): yield "lf" -class LDSTFFRc1RM(FFRc1BaseRM, LDSTImmBaseRM): +class LDSTFFRc1RM(FFRc1BaseRM, VLiBaseRM, LDSTImmBaseRM): """ld/st immediate&indexed: Rc=1: ffirst CR sel""" VLi: BaseRM.mode[0] inv: BaseRM.mode[2] @@ -2236,7 +2239,7 @@ class LDSTFFRc1RM(FFRc1BaseRM, LDSTImmBaseRM): yield from super().specifiers(record=record, mode="ff") -class LDSTFFRc0RM(FFRc0BaseRM, ElsBaseRM, LDSTImmBaseRM): +class LDSTFFRc0RM(FFRc0BaseRM, VLiBaseRM, ElsBaseRM, LDSTImmBaseRM): """ld/st immediate&indexed: Rc=0: ffirst z/nonz""" VLi: BaseRM.mode[0] inv: BaseRM.mode[2] @@ -2346,7 +2349,7 @@ class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CRO # Please revisit this code; there is an inactive sketch below. class CROpFF5RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, CROpBaseRM): """cr_op: ffirst 5-bit mode""" - VLi: BaseRM[20] + VLi: BaseRM[19] inv: BaseRM[21] CR: BaseRM[22, 23] dz: BaseRM[22] @@ -3272,11 +3275,10 @@ class RMSelector: table = ( (0b000000, 0b111000, "simple"), # simple (no Rc) (0b001000, 0b111100, "mr"), # mapreduce (no Rc) - (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1 - (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0 + (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1 + (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0 (0b100000, 0b110000, "sat"), # saturation (no Rc) (0b001100, 0b111100, "rsvd"), # reserved - (0b110000, 0b110000, "rsvd"), # reserved ) mode = int(self.insn.prefix.rm.normal.mode) search = ((mode << 1) | self.record.Rc) diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 6b9c9b51..2ebd5027 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -446,11 +446,10 @@ def extra_classifier(insn_name, value, name, res, regs): res['0'] = 'd:RA;s:RA' # RA: Rdest_EXTRA3 / Rsrc_EXTRA3 res['1'] = sRS # RS: Rdsrc1_EXTRA3 elif 'st' in insn_name and 'x' in insn_name: # stwux - res['Etype'] = 'EXTRA2' # RM EXTRA2 type - res['0'] = 'd:RA' # RA: Rdest1_EXTRA2 - # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2 - res['1'] = "%s;%s" % (sRS, 's:RA') - res['2'] = 's:RB' # RB: Rsrc2_EXTRA2 + res['Etype'] = 'EXTRA3' # RM EXTRA2 type + # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2 / Rdest + res['0'] = "%s;s:RA;d:RA" % (sRS) + res['1'] = 's:RB' # RB: Rsrc2_EXTRA2 elif 'u' in insn_name: # ldux etc. res['Etype'] = 'EXTRA2' # RM EXTRA2 type res['0'] = dRT # RT: Rdest1_EXTRA2 @@ -600,7 +599,6 @@ def extra_classifier(insn_name, value, name, res, regs): res['0'] = 's:FRT;d:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA2 res['1'] = 's:FRB' # FRB: Rsrc1_EXTRA2 res['2'] = 's:FRA' # FRA: Rsrc2_EXTRA2 - res['3'] = '' # empty elif regs == ['RA', 'RB', 'RC', 'RT', '', '']: # madd* res['0'] = 'd:RT' # RT,CR0: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 @@ -615,12 +613,10 @@ def extra_classifier(insn_name, value, name, res, regs): res['0'] = 's:RT;d:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2 - res['3'] = '' # empty elif regs == ['RA', 'RB', 'RT', 'RT', '', '']: # maddsubrs res['0'] = 's:RT;d:RT' # RT: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2 - res['3'] = '' # empty elif insn_name == 'isel': res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 -- 2.30.2