From a9b11d7c83a060e59185636711c3ffa4f1c76591 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 21:58:59 +0100 Subject: [PATCH] Added CONSTMSK and CONSTVAL feature to techmap --- passes/techmap/techmap.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index eb044d6fe..da87c3ab7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -201,6 +201,7 @@ struct TechmapWorker bool did_something = false; std::vector cell_names; + SigMap sigmap(module); for (auto &cell_it : module->cells) cell_names.push_back(cell_it.first); @@ -254,6 +255,22 @@ struct TechmapWorker if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); + + for (auto conn : cell->connections) { + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0); + parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + if (bit.wire != NULL) + bit = RTLIL::SigBit(RTLIL::State::Sx); + parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); + } + } } std::pair> key(tpl_name, parameters); @@ -431,6 +448,12 @@ struct TechmapPass : public Pass { log(" When a parameter with this name exists, it will be set to the type name\n"); log(" of the cell that matches the module.\n"); log("\n"); + log(" _TECHMAP_CONSTMSK__\n"); + log(" _TECHMAP_CONSTVAL__\n"); + log(" When this pair of parameters is available in a module for a port, then\n"); + log(" former has a 1-bit for each constant input bit and the latter has the\n"); + log(" value for this bit. The unused bits of the latter are set to undef (x).\n"); + log("\n"); log("When a module in the map file has a parameter where the according cell in the\n"); log("design has a port, the module from the map file is only used if the port in\n"); log("the design is connected to a constant value. The parameter is then set to the\n"); -- 2.30.2