From a9b42161c0540b0c6b86541e6c764a1b8a0ef914 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 15:29:34 +0200 Subject: [PATCH] litesata: pep8 (E222) --- misoclib/mem/litesata/example_designs/make.py | 2 +- misoclib/mem/litesata/test/hdd.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py index 171be407..2a8b5829 100755 --- a/misoclib/mem/litesata/example_designs/make.py +++ b/misoclib/mem/litesata/example_designs/make.py @@ -72,7 +72,7 @@ if __name__ == "__main__": platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) platform = platform_module.Platform(**platform_kwargs) - build_name = top_class.__name__.lower() + "-" + platform_name + build_name = top_class.__name__.lower() + "-" + platform_name top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index 643dfac3..50663442 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -433,7 +433,7 @@ class CommandLayer(Module): resp = None if isinstance(fis, FIS_REG_H2D): if fis.command == regs["WRITE_DMA_EXT"]: - resp = self.hdd.write_dma_callback(fis) + resp = self.hdd.write_dma_callback(fis) elif fis.command == regs["READ_DMA_EXT"]: resp = self.hdd.read_dma_callback(fis) elif isinstance(fis, FIS_DATA): -- 2.30.2