From a9b4c221a1f12f03e2e521c7efd7f5ad48adfb82 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 13:00:12 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index cc7f4098f..32a3504fc 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -500,6 +500,23 @@ concept needs no branches, no complex Register Hazard Management because it is down to the programmer (or, the compiler), to ensure data overlaps do not occur. +Zero-Overhead Loop Control takes this basic "single loop" concept +way further: both nested loops and conditional exit are included, +but also arbitrary control-jumping from the current inner loop +out to an entirely different loop, all based on conditions determined +dynamically at runtime. + +Even when deployed on as basic a CPU as a single-issue in-order RISC +core, the performance and power-savings were astonishing: between 20 +and **80** reduction in algorithm completion times were achieved compared +to a more traditional branch-speculative in-order RISC CPU. MPEG +Decode, the target algorithm specifically picked by the researcher +due to its high complexity with 6-deep nested loops and conditional +execution that frequently jumped in and out of at least 2 loops, +came out with an astonishing 43% improvement in completion time. 43% +less instructions executed is an almost unheard-of level of optimisation: +most ISA designers are elated if they can achieve 5 to 10%. + **OpenCAPI and Extra-V** **Snitch** -- 2.30.2